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general description the MAX17030/max17036 are 3/2-phase interleaved quick-pwm? step-down vid power-supply controllers for imvp-6.5 notebook cpus. two integrated drivers and the option to drive a third phase using an external driver such as the max8791 allow for a flexible 3/2-phase con- figuration depending on the cpu being supported. true out-of-phase operation reduces input ripple-current requirements and output-voltage ripple while easing component selection and layout difficulties. the quick- pwm control provides instantaneous response to fast load-current steps. active voltage positioning reduces power dissipation and bulk output capacitance require- ments and allows ideal positioning compensation for tan- talum, polymer, or ceramic bulk output capacitors. the MAX17030/max17036 are intended for bucking down the battery directly to create the core voltage. the single-stage conversion method allows this device to directly step down high-voltage batteries for the highest possible efficiency. a slew-rate controller allows controlled transitions between vid codes. a thermistor-based temperature sensor provides programmable thermal protection. an output current monitor provides an analog current out- put proportional to the sum of the inductor currents, which in steady state is the same as the current con- sumed by the cpu. applications imvp-6.5 sv and xe core power supplies high-current voltage-positioned step-down converters 3 to 4 li+ cells battery to cpu core supply converters notebooks/desktops/servers features triple/dual-phase quick-pwm controllers 2 internal drivers + 1 external driver ?.5% v out accuracy over line, load, and temperature 7-bit imvp-6.5 dac dynamic phase selection optimizes active/sleep efficiency transient phase overlap reduces output capacitance transient suppression feature (max17036 only) integrated boost switches active voltage positioning with adjustable gain accurate lossless current balance and current limit remote output and ground sense adjustable output slew-rate control power-good (imvpok), clock enable ( clken ), and thermal-fault ( vrhot ) outputs imvp-6.5 power sequencing and timing compliant output current monitor (imon) drives large synchronous rectifier fets 7v to 26v battery input range adjustable switching frequency (600khz max) undervoltage, overvoltage, and thermal-fault protection MAX17030/max17036 1/2/3-phase quick-pwm imvp-6.5 vid controllers ________________________________________________________________ maxim integrated products 1 bst1 lx1 dl1 v dd dh2 lx2 bst2 vrhot dl2 dh1 thrm imon ilim time v cc fb fbac gnds csp3 csn3 shdn ton drskp pwm3 dprslpvr psi csp2 csn2 csp1 d6 d5 d4 d3 d2 d1 d0 pgd_in csn1 pwrgd MAX17030 max17036 thin qfn 5mm x 5mm + top view 35 36 34 33 12 11 13 14 12 4 567 27 28 29 30 26 24 23 22 3 25 37 38 39 40 32 15 31 16 17 18 19 20 8910 21 clken pin configuration ordering information 19-4577; rev 0; 4/09 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. evaluation kit available part temp range pin-package MAX17030 gtl+ -40c to +105c 40 tqfn-ep* max17036 gtl+ -40c to +105c 40 tqfn-ep* + denotes a lead-free(pb)/rohs-compliant package. * ep = exposed pad. quick-pwm is a trademark of maxim integrated products, inc.
MAX17030/max17036 1/2/3-phase quick-pwm imvp-6.5 vid controllers 2 _______________________________________________________________________________________ absolute maximum ratings (note 1) electrical characteristics (circuit of figure 1, v in = 10v, v cc = v dd = v shdn = v pgd_in = v psi = v ilim = 5v, v dprslpvr = v gnds = 0, v csp_ = v csn_ = 1.0000v, fb = fbac, r fbac = 3.57k ? from fbac to csn_, [d6Cd0] = [0101000]; t a = 0? to +85? , unless otherwise noted. typical values are at t a = +25c.) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v cc , v dd to gnd .....................................................-0.3v to +6v d0Cd6, pgd_in, psi , dprslpvr to gnd ...............-0.3v to +6v csp_, csn_, thrm, ilim to gnd............................-0.3v to +6v pwrgd, clken , vr_hot to gnd..........................-0.3v to +6v fb, fbac, imon, time to gnd .................-0.3v to (v cc + 0.3v) shdn to gnd (note 2)...........................................-0.3v to +30v ton to gnd ...........................................................-0.3v to +30v gnds to gnd .......................................................-0.3v to +0.3v dl1, dl2, pwm3, drskp to gnd .............-0.3v to (v dd + 0.3v) bst1, bst2 to gnd ...............................................-0.3v to +36v bst1, bst2 to v dd .................................................-0.3v to +30v lx1 to bst1..............................................................-6v to +0.3v lx2 to bst2..............................................................-6v to +0.3v dh1 to lx1 ..............................................-0.3v to (v bst1 + 0.3v) dh2 to lx2 ..............................................-0.3v to (v bst2 + 0.3v) continuous power dissipation (40-pin, 5mm x 5mm tqfn) up to +70c ..............................................................1778mw derating above +70c ..........................................22.2mw/c operating temperature range .........................-40c to +105c junction temperature ......................................................+150c storage temperature range .............................-65c to +165c lead temperature (soldering, 10s) .................................+300c parameter symbol conditions min typ max units pwm controller v cc , v dd 4.5 5.5 input voltage range v in 7 26 v dac codes from 0.8125v to 1.5000v -0.5 +0.5 % dac codes from 0.3750v to 0.8000v -7 +7 fb output voltage accuracy v fb measured at fb with respect to gnds; includes load- regulation error (note 3) dac codes from 0 to 0.3625v -20 +20 mv boot voltage v boot 1.094 1.100 1.106 v line regulation error v cc = 4.5v to 5.5v, v in = 4.5v to 26v 0.1 % fb input bias current t a = +25 c -0.1 +0.1 a gnds input range -200 +200 mv gnds gain a gnds v out / v gnds 0.97 1.00 1.03 v/v gnds input bias current i gnds t a = +25 c -0.5 +0.5 a time regulation voltage v time r time = 147k 1.985 2.000 2.015 v r time = 147k (6.08mv/s nominal) -10 +10 r time = 35.7k (25mv/s nominal) to 178k (5mv/s nominal) -15 +15 time slew-rate accuracy soft-start and soft-shutdown: r time = 35.7k (6.25mv/s nominal) to 178k (1.25mv/s nominal) -20 +20 % note 1: absolute maximum ratings valid using 20mhz bandwidth limit. note 2: shdn might be forced to 12v for the purpose of debugging prototype breadboards using the no-fault test mode. internal bst switches are disabled as well. use external bst diodes when shdn is forced to 12v.
MAX17030/max17036 1/2/3-phase quick-pwm imvp-6.5 vid controllers _______________________________________________________________________________________ 3 parameter symbol conditions min typ max units r ton = 96.75k (600khz per phase), 167ns nominal -15 +15 r ton = 200k (300khz per phase), 333ns nominal -10 +10 on-time accuracy t on v in = 10v, v fb = 1.0v, measured at dh1, dh2, and pwm3 (note 4) r ton = 303.25k (200khz per phase), 500ns nominal -15 +15 % minimum off-time t off(min) measured at dh1, dh2, and pwm3 (note 4) 300 375 ns ton shutdown input current i ton,sdn shdn = gnd, v in = 26v, v cc = v dd = 0 or 5v, t a = +25 c 0.01 0.1 a bias currents quiescent supply current (v cc ) i cc measured at v cc , v dprslpvr = 5v, fb forced above the regulation point 3.5 7 ma quiescent supply current (v dd ) i dd measured at v dd , v dprslpvr = 0, fb forced above the regulation point, t a = +25 c 0.02 1 a shutdown supply current (v cc ) i cc,sdn measured at v cc , shdn = gnd, t a = +25 c 0.01 1 a shutdown supply current (v dd ) i dd,sdn measured at v dd , shdn = gnd, t a = +25 c 0.01 1 a fault protection skip mode after output reaches the regulation voltage or pwm mode; measured at fb with respect to the voltage target set by the vid code (see table 4) 250 300 350 mv soft-start, soft-shutdown, skip mode, and output have not reached the regulation voltage; measured at fb 1.45 1.50 1.55 output overvoltage-protection threshold v ovp minimum ovp threshold; measured at fb 0.8 v output overvoltage- propagation dela y t ovp fb forced 25mv above trip threshold 10 s output undervoltage- protection threshold v uvp measured at fb with respect to the voltage target set by the vid code (see table 4) -450 -400 -350 mv output undervoltage- propagation dela y t uvp fb forced 25mv below trip threshold 10 s clken startup delay and boot time period t boot measured from the time when fb reaches the boot target voltage (note 3) 20 60 100 s electrical characteristics (continued) (circuit of figure 1, v in = 10v, v cc = v dd = v shdn = v pgd_in = v psi = v ilim = 5v, v dprslpvr = v gnds = 0, v csp_ = v csn_ = 1.0000v, fb = fbac, r fbac = 3.57k ? from fbac to csn_, [d6Cd0] = [0101000]; t a = 0? to +85? , unless otherwise noted. typical values are at t a = +25c.)
MAX17030/max17036 1/2/3-phase quick-pwm imvp-6.5 vid controllers 4 _______________________________________________________________________________________ electrical characteristics (continued) (circuit of figure 1, v in = 10v, v cc = v dd = v shdn = v pgd_in = v psi = v ilim = 5v, v dprslpvr = v gnds = 0, v csp_ = v csn_ = 1.0000v, fb = fbac, r fbac = 3.57k ? from fbac to csn_, [d6Cd0] = [0101000]; t a = 0? to +85? , unless otherwise noted. typical values are at t a = +25c.) parameter symbol conditions min typ max units pwrgd startup delay measured at startup from the time when clken goes low 3 6.5 10 ms lower threshold, falling edge (undervoltage) -350 -300 -250 clken and pwrgd threshold measured at fb with respect to the voltage target set by the vid code (see table 4), 20mv hysteresis (typ) upper threshold, rising edge (overvoltage) +150 +200 +250 mv clken and pwrgd delay fb forced 25mv outside the pwrgd trip thresholds 10 s clken and pwrgd transition blanking time (vid transitions) t blank measured from the time when fb reaches the target voltage (note 3) 20 s clken , pwrgd output low voltage low state, i sink = 3ma 0.4 v clken , pwrgd leakage current high-z state, pin forced to 5v, t a = +25 c 1 a csn1 pulldown resistance in uvlo and shutdown shdn = gnd, measured after soft- shutdown completed (dl = low) 8 v cc undervoltage-lockout threshold v uvlo(vcc) rising edge, 65mv typical hysteresis, controller disabled below this level 4.05 4.27 4.48 v thermal protection vrhot trip threshold measured at thrm with respect to v cc ; falling edge, typical hysteresis = 75mv 29 30 31 % vrhot delay t vrhot thrm forced 25mv below the vrhot trip threshold, falling edge 10 s vrhot output on-resistance r on( vrhot ) low state 2 8 vrhot leakage current high-z state, vrhot forced to 5v, t a = +25c 1 a thrm input leakage i thrm v thrm = 0 to 5v, t a = +25c -0.1 +0.1 a thermal-shutdown threshold t shdn typical hysteresis = 15c +160 c valley current limit, droop, current balance, and current monitor v time - v ilim = 100mv 7 10 13 v time - v ilim = 500mv 45 50 55 current-limit threshold voltage (positive) v limit v csp_ - v csn_ ilim = v cc 20 22.5 25 mv current-limit threshold voltage (negative) accuracy v limit(neg) v csp_ - v csn_ , nominally -125% of v limit -4 +4 mv current-limit threshold voltage (zero crossing) v zx v gnd - v lx_ , v dprslpvr = 5v 0 mv csp_, csn_ common-mode input range 0 2 v
MAX17030/max17036 1/2/3-phase quick-pwm imvp-6.5 vid controllers _______________________________________________________________________________________ 5 electrical characteristics (continued) (circuit of figure 1, v in = 10v, v cc = v dd = v shdn = v pgd_in = v psi = v ilim = 5v, v dprslpvr = v gnds = 0, v csp_ = v csn_ = 1.0000v, fb = fbac, r fbac = 3.57k from fbac to csn_, [d6Cd0] = [0101000]; t a = 0? to +85? , unless otherwise noted. typical values are at t a = +25c.) parameter symbol conditions min typ max units phases 2, 3 disable threshold measured at csp2, csp3 3 v cc - 1 v cc - 0.4 v csp_, csn_ input current i csp , i csn t a = +25 c -0.2 +0.2 a ilim input current i ilim t a = +25 c -0.1 +0.1 a t a = +25c -0.5 +0.5 droop amplifier offset (1/n) x (v csp_ - v csn_ ) at i fbac = 0; indicates summation over all power-up enabled phases from 1 to n, n = 3 t a = 0 c to +85c -0.75 +0.75 mv/ phase droop amplifier transconductance g m(fbac) i fbac / [ (v csp_ - v csn_ )]; indicates summation over all power-up enabled phases from 1 to n, n = 3, v fbac = v csn_ = 0.45v to 1.5v 393 400 406 s current-monitor offset (1/n) x (v csp_ - v csn_ ) at i imon = 0, indicates summation over all power-up enabled phases from 1 to n, n = 3 -1.1 +1 mv/ phase current-monitor transconductance g m(imon) i imon / [ (v csp_ - v csn_ )]; indicates summation over all power-up enabled phases from 1 to n, n = 3, v csn_ = 0.45v to 1.5v 1.552 1.6 1.648 ms gate drivers high state (pullup) 0.9 2.5 dh_ gate-driver on-resistance r on(dh) bst_ - lx_ forced to 5v low state (pulldown) 0.7 2 high state (pullup) 0.7 2 dl_ gate-driver on-resistance r on(dl) low state (pulldown) 0.25 0.7 dh_ gate-driver source current i dh(source) dh_ forced to 2.5v, bst_ - lx_ forced to 5v 2.2 a dh_ gate-driver sink current i dh(sink) dh_ forced to 2.5v, bst_ - lx_ forced to 5v 2.7 a dl_ gate-driver source current i dl(source) dl_ forced to 2.5v 2.7 a dl_ gate-driver sink current i dl(sink) dl_ forced to 2.5v 8 a dl_ falling, c dl_ = 3nf 20 dl_ transition time dl rising, c dl_ = 3nf 20 ns dh_ falling, c dh_ = 3nf 20 dh_ transition time dh_ rising, c dh_ = 3nf 20 ns internal bst_ switch on-resistance r on(bst) i bst_ = 10ma 10 20
MAX17030/max17036 1/2/3-phase quick-pwm imvp-6.5 vid controllers 6 _______________________________________________________________________________________ electrical characteristics (continued) (circuit of figure 1, v in = 10v, v cc = v dd = v shdn = v pgd_in = v psi = v ilim = 5v, v dprslpvr = v gnds = 0, v csp_ = v csn_ = 1.0000v, fb = fbac, r fbac = 3.57k ? from fbac to csn_, [d6Cd0] = [0101000]; t a = 0? to +85? , unless otherwise noted. typical values are at t a = +25c.) parameter symbol conditions min typ max units pwm3, drskp outputs pwm3, drskp output high voltages i source = 3ma v dd - 0.4v v pwm3, drskp output low voltages i sink = 3ma 0.4 v logic and i/o logic-input high voltage v ih shdn , pgd_in 2.3 v logic-input low voltage v il shdn , pgd_in 1.0 v low-voltage logic-input high voltage v ihlv psi , d0Cd6, dprslpvr 0.67 v low-voltage logic-input low voltage v illv psi , d0Cd6, dprslpvr 0.33 v logic input current t a = +25 c; shdn , dprslpvr, pgd_in, psi , d0Cd6 = 0 or 5v -1 +1 a electrical characteristics (circuit of figure 1, v in = 10v, v cc = v dd = v shdn = v pgd_in = v psi = v ilim = 5v, v dprslpvr = v gnds = 0, v csp_ = v csn_ = 1.0000v, fb = fbac, r fbac = 3.57k ? from fbac to csn_, [d6Cd0] = [0101000]; t a = -40 o c to +105? , unless otherwise noted.) (note 5) parameter symbol conditions min typ max units pwm controller v cc , v dd 4.5 5.5 input voltage range v in 7 26 v dac codes from 0.8125v to 1.5000v -0.75 +0.75 % dac codes from 0.3750v to 0.8000v -10 +10 fb output-voltage accuracy v fb measured at fb with respect to gnds, includes load- regulation error (note 3) dac codes from 0 to 0.3625v -25 +25 mv boot voltage v boot 1.085 1.115 v gnds input range -200 +200 mv gnds gain a gnds v out / v gnds 0.95 1.05 v/v time regulation voltage v time r time = 147k 1.985 2.015 v r time = 147k (6.08mv/s nominal) -10 +10 r time = 35.7k (25mv/s nominal) to 178k (5mv/s nominal) -15 +15 time slew-rate accuracy soft-start and soft-shutdown: r time = 35.7k (6.25mv/s nominal) to 178k (1.25mv/s nominal) -20 +20 %
MAX17030/max17036 1/2/3-phase quick-pwm imvp-6.5 vid controllers _______________________________________________________________________________________ 7 electrical characteristics (continued) (circuit of figure 1, v in = 10v, v cc = v dd = v shdn = v pgd_in = v psi = v ilim = 5v, v dprslpvr = v gnds = 0, v csp_ = v csn_ = 1.0000v, fb = fbac, r fbac = 3.57k ? from fbac to csn_, [d6Cd0] = [0101000]; t a = -40 o c to +105? , unless otherwise noted.) (note 5) parameter symbol conditions min typ max units r ton = 96.75k (600khz per phase), 167ns nominal -15 +15 r ton = 200k (300khz per phase), 333ns nominal -10 +10 on-time accuracy t on v in = 10v, v fb = 1.0v, measured at dh1, dh2, and pwm3 (note 4) r ton = 303.25k (200khz per phase), 500ns nominal -15 +15 % minimum off-time t off(min) measured at dh1, dh2, and pwm3 (note 4) 400 ns bias currents quiescent supply current (v cc ) i cc measured at v cc , dprslpvr = 5v, fb forced above the regulation point 7 ma fault protection skip mode after output reaches the regulation voltage or pwm mode; measured at fb with respect to the voltage target set by the vid code (see table 4) 250 350 mv output overvoltage-protection threshold v ovp soft-start, soft-shutdown, skip mode, and output have not reached the regulation voltage; measured at fb 1.45 1.55 v output undervoltage-protection threshold v uvp measured at fb with respect to the voltage target set by the vid code (see table 4) -450 -350 mv clken startup delay and boot time period t boot measured from the time when fb reaches the boot target voltage (note 3) 20 100 s pwrgd startup delay measured at startup from the time when clken goes low 3 10 ms lower threshold, falling edge (undervoltage) -350 -250 clken and pwrgd threshold measured at fb with respect to the voltage target set by the vid code (see table 4), 20mv hysteresis (typ) upper threshold, rising edge (overvoltage) +150 +250 mv clken , pwrgd output low voltage low state, i sink = 3ma 0.4 v v cc undervoltage-lockout threshold v uvlo(vcc) rising edge, 65mv typical hysteresis, controller disabled below this level 4.05 4.5 v thermal protection vrhot trip threshold measured at thrm with respect to v cc , falling edge, typical hysteresis = 75mv 29 31 % vrhot output on-resistance r on( vrhot ) low state 8
MAX17030/max17036 1/2/3-phase quick-pwm imvp-6.5 vid controllers 8 _______________________________________________________________________________________ parameter symbol conditions min typ max units valley current limit, droop, current balance, and current monitor v time - v ilim = 100mv 7 13 v time - v ilim = 500mv 45 55 current-limit threshold voltage (positive) v limit v csp_ - v csn_ ilim = v cc 20 25 mv current-limit threshold voltage (negative) accuracy v limit(neg) v csp_ - v csn_ , nominally -125% of v limit -4 +4 mv csp_, csn_ common-mode input range 0 2 v phases 2, 3 disable threshold measured at csp2, csp3 3 v cc - 0.4 v droop amplifier offset (1/n) x (v csp_ - v csn_ ) at i fbac = 0; indicates summation over all power-up enabled phases from 1 to n, n = 3 -1 +1 mv/ phase droop amplifier transconductance g m(fbac) i fbac / [ (v csp_ - v csn_ )]; indicates summation over all power-up enabled phases from 1 to n, n = 3, v fbac = v csn_ = 0.45v to 1.5v 390 407 s current-monitor offset (1/n) x (v csp_ - v csn_ ) at i fbac = 0; indicates summation over all power-up enabled phases from 1 to n, n = 3 -1.5 +1.5 mv/ phase current-monitor transconductance g m(imon) i imon / [ (v csp_ - v csn_ )]; indicates summation over all power-up enabled phases from 1 to n, n = 3, v csn_ = 0.45v to 1.5v 1.536 1.664 ms gate drivers high state (pullup) 2.5 dh_ gate-driver on-resistance r on(dh) bst_ C lx_ forced to 5v low state (pulldown) 2 high state (pullup) 2 dl_ gate-driver on-resistance r on(dl) low state (pulldown) 0.7 internal bst_ switch on-resistance r on(bst) i bst- = 10ma 20 pwm3, drskp outputs pwm3, drskp output high voltages i source = 3ma v dd - 0.4v v pwm3, drskp output low voltages i sink = 3ma 0.4 v logic and i/o logic-input high voltage v ih shdn , pgd_in 2.3 v logic-input low voltage v il shdn , pgd_in 1.0 v low-voltage logic-input high voltage v ihlv psi , d0Cd6, dprslpvr 0.67 v low-voltage logic-input low voltage v illv psi , d0Cd6, dprslpvr 0.33 v electrical characteristics (continued) (circuit of figure 1, v in = 10v, v cc = v dd = v shdn = v pgd_in = v psi = v ilim = 5v, v dprslpvr = v gnds = 0, v csp_ = v csn_ = 1.0000v, fb = fbac, r fbac = 3.57k from fbac to csn_, [d6Cd0] = [0101000]; t a = -40 o c to +105? , unless otherwise noted.) (note 5)
note 3: the equation for the target voltage v target is: v target = the slew-rate-controlled version of v dac , where v dac = 0 for shutdown v dac = v boot during imvp-6.5 startup v dac = v vid otherwise (the v vid voltages for all possible vid codes are given in table 4). in pulse-skipping mode, the output rises by approximately 1.5% when transitioning from continuous conduction to no load. note 4: on-time and minimum off-time specifications are measured from 50% to 50% at the dh_ pin, with lx_ forced to 0v, bst_ forced to 5v, and a 500pf capacitor from dh_ to lx_ to simulate external mosfet gate capacitance. actual in-circuit times might be different due to mosfet switching speeds. note 5: specifications to -40c and +105c are guaranteed by design, not production tested. MAX17030/max17036 1/2/3-phase quick-pwm imvp-6.5 vid controllers _______________________________________________________________________________________ 9 efficiency vs. load current (v out(hfm) = 0.95v) MAX17030 toc01 load current (a) efficiency (%) 10 1 30 40 50 60 70 80 90 100 20 0.1 100 12v 20v 7v output voltage vs. load current (v out(hfm) = 0.95v) MAX17030 toc02 load current (a) output voltage (v) 50 60 20 30 40 0.85 0.90 0.95 1.00 0.80 010 70 efficiency vs. load current (v out(lfm) = 0.875v) MAX17030 toc03 load current (a) efficiency (%) 10 1 60 70 80 90 50 0.1 100 12v 20v 7v skip mode pwm mode output voltage vs. load current (v out(lfm) = 0. 8 75v) MAX17030 toc04 load current (a) output voltage (v) 15 510 0.84 0.85 0.87 0.86 0.88 0.89 0.90 0.83 020 2-phase pwm mode 1-phase skip mode switching frequency vs. load current MAX17030 toc05 load current (a) switching frequency (khz) 30 10 20 100 50 150 250 200 300 350 400 0 050 40 v out(hfm) = 0.95v v out(lfm) = 0.875v dprslpvr = v cc dprslpvr = gnd v out(hfm) = 0.95v no-load supply current vs. input voltage MAX17030 toc06 input voltage (v) supply current (ma) 15 912 0.1 1 10 100 1000 0.01 621 18 i in i in i cc + i dd i cc + i dd dprslpvr = v cc dprslpvr = gnd typical operating characteristics (circuit of figure 1. v in = 12v, v cc = v dd = 5v, shdn = v cc , d0Cd6 set for 0.95v, t a = +25c, unless otherwise specified.) electrical characteristics (continued)
MAX17030/max17036 1/2/3-phase-quick-pwm imvp-6.5 vid controllers 10 ______________________________________________________________________________________ typical operating characteristics (continued) (circuit of figure 1. v in = 12v, v cc = v dd = 5v, shdn = v cc , d0Cd6 set for 0.95v, t a = +25c, unless otherwise specified.) current balance vs. load current MAX17030 toc07 load current (a) sense voltage (mv) sense voltage difference (mv) 30 40 10 20 5 10 15 20 0 -0.1 0 0.1 0.2 -0.2 070 60 50 v out = 0.95v v csp1 - v csn1 v csp2 - v csn2 v cs3 - v cs1 v cs2 - v cs1 v csp3 - v csn3 i imon vs. load current MAX17030 toc08 v csp - csn (mv) imon ( a) 30 10 20 20 40 60 80 100 0 060 50 40 v out = 0.95v dprslpvr = gnd 0. 8 125v output voltage distribution MAX17030 toc09 output voltage (v) sample percentage (%) 0.8085 0.8095 0.8105 0.8115 0.8125 0.8135 0.8145 0.8155 0.8165 0.8175 0.8075 20 10 30 40 50 60 70 0 +85 c +25 c sample size = 100 g m(fb) transconductance distribution MAX17030 toc10 tranconductance ( s) sample percentage (%) 392 394 396 398 400 402 404 406 408 410 390 20 10 30 40 50 60 70 0 +85 c +25 c sample size = 100 g m(imon) transconductance distribution MAX17030 toc11 tranconductance ( s) sample percentage (%) 1560 1570 1580 1590 1600 1610 1620 1630 1640 1650 1550 15 5 10 20 25 30 35 40 0 +85 c +25 c sample size = 100
MAX17030/max17036 1/2/3-phase-quick-pwm imvp-6.5 vid controllers ______________________________________________________________________________________ 11 soft-start waveform (up to clken) MAX17030 toc12 200 s/div a. shdn, 5v/div b. clken, 10v/div c. v out , 500mv/div 0 0 0 0 0 0 e d c b a f 3.3v 0.95v 3.3v d. i lx1 , 10a/div e. i lx2 , 10a/div f. i lx3 , 10a/div i out , 15a soft-start waveform (up to pwrgd) MAX17030 toc13 1ms/div a. shdn, 5v/div b. clken, 6.6v/div c. pwrgd, 10v/div d. v out , 1v/div 0 0 0 0 0 0 0 e d c b a f g 3.3v 0.95v 3.3v 3.3v e. dl1, 10v/div f. dl2, 10v/div g. dl3, 10v/div i out , 15a shutdown waveform MAX17030 toc14 200 s/div a. shdn, 5v/div b. pwrgd, 10v/div c. clken, 10v/div d. v out , 500mv/div 0 0 0 0 0 0 0 e d c b a f g 3.3v 0.95v 3.3v 3.3v e. dl1, 10v/div f. dl2, 10v/div g. dl3, 10v/div load-transient response (hfm mode) MAX17030 toc15 20 s/div a. i out = 7a - 59a b. v out , 50mv/div e d c b a 59a 0.84v 7a 0.935v c. i lx1 , 20a/div d. i lx2 , 20a/div e. i lx3 , 20a/div typical operating characteristics (continued) (circuit of figure 1. v in = 12v, v cc = v dd = 5v, shdn = v cc , d0Cd6 set for 0.95v, t a = +25c, unless otherwise specified.)
MAX17030/max17036 1/2/3-phase quick-pwm imvp-6.5 vid controllers 12 ______________________________________________________________________________________ pin description pin name function 1 csn3 negative input of the output current sense of phase 3. this pin should be connected to the negative side of the output current-sensing resistor or the filtering capacitor if the dc resistance of the output inductor is utilized for current sensing. 2 csp3 positive input of the output current sense of phase 3. this pin should be connected to the positive side of the output current-sensing resistor or the filtering capacitor if the dc resistance of the output inductor is utilized for current sensing. to disable phase 3, connect csp3 to v cc and csn3 to gnd. 3 thrm input of internal comparator. connect the output of a resistor- and thermistor-divider (between v cc and gnd) to thrm. select the components such that the voltage at thrm falls below 1.5v (30% of v cc ) at the desired high temperature. 4 imon current monitor output pin. the output current at this pin is: i imon = g m(imon) x v(csp_,csn_) where g m(imon) = 1.6ms typical and denotes summation over all enabled phases. an external resistor r imon between imon and gnds sets the current-monitor output voltage: v imon = i load x r sense x g m(imon) x r imon where r sense is the value of the effective current-sense resistance. choose r imon such that v imon does not exceed 900mv at the maximum expected load current i max . imon is high impedance when the MAX17030/max17036 are in shutdown. 5 ilim current-limit adjust input. the valley positive current-limit threshold voltages at v(csp_,csn_) are precisely 1/10 the differential voltage v(time,ilim) over a 0.1v to 0.5v range of v(time,ilim). the valley negative current-limit thresholds are typically -125% of the corresponding valley positive current-limit thresholds. connect ilim to v cc to get the default current-limit threshold setting of 22.5mv typ. 6 time slew-rate adjustment pin. the total resistance r time from time to gnd sets the internal slew rate: slew rate = (12.5mv/s) x (71.5k /r time ) where r time is between 35.7k and 178k . this normal slew rate applies to transitions into and out of the low-power pulse-skipping modes and to the transition from boot mode to vid. the slew rate for startup and for entering shutdown is always 1/4 of normal. if the vid dac inputs are clocked, the slew rate for all other vid transitions is set by the rate at which they are clocked, up to a maximum slew rate equal to the normal slew rate defined above. 7 v cc controller supply voltage. connect to a 4.5v to 5.5v source. bypass to gnd with 1f minimum. 8 fb feedback voltage input. the voltage at the fb pin is compared with the slew-rate-controlled target voltage by the error comparator (fast regulation loop), as well as by the internal voltage integrator (slow, accurate regulation loop). having sufficient ripple signal at fb that is in phase with the sum of the inductor currents is essential for cycle-by-cycle stability. the external connections and compensation at fb depend on the desired dc and transient (ac) droop values. if dc droop = ac droop, then short fb to fbac. to disable dc droop, connect fb to the remote-sensed output voltage through a resistor r and feed forward the fbac ripple to fb through capacitor c, where the r x c time constant should be at least 3x the switching period per phase.
MAX17030/max17036 1/2/3-phase quick-pwm imvp-6.5 vid controllers ______________________________________________________________________________________ 13 pin description (continued) pin name function 9 fbac output of the voltage-positioning transconductance amplifier. connect a resistor r fbac between fbac and the positive side of the feedback remote sense to set the transient (ac) droop based on the stability, load-transient response, and voltage-positioning gain requirements: r fbac = r droop,ac /[r sense x g m(fbac) ] where r droop,ac is the transient (ac) voltage-positioning slope that provides an acceptable tradeoff between stability and load-transient response, g m(fbac) = 400s typ, and r sense is the effective current-sense resistance that is used to provide the (csp_, csn_) current-sense voltages. a minimum r droop,ac value is required for stability, but if there are no ceramic output capacitors used, then the minimum requirement applies to r esr + r droop,ac , where r esr is the effective esr of the output capacitors. if lossless sensing (inductor dcr sensing) is used, use a thermistor-resistor network to minimize the temperature dependence of the voltage-positioning slope. fbac is high impedance in shutdown. 10 gnds feedback remote-sense input, negative side. normally connected to gnd directly at the load. gnds internally connects to a transconductance amplifier that fine tunes the output voltage compensating for voltage drops from the regulator ground to the load ground. 11 csn2 negative input of the output current sense of phase 2. this pin should be connected to the negative side of the output current-sensing resistor or the filtering capacitor if the dc resistance of the output inductor is utilized for current sensing. 12 csp2 positive input of the output current sense of phase 2. this pin should be connected to the positive side of the output current-sensing resistor or the filtering capacitor if the dc resistance of the output inductor is utilized for current sensing. to disable phase 2, connect csp2 to v cc and csn2 to gnd. 13 shdn shutdown control input. connect to v cc for normal operation. connect to ground to put the ic into the 1a (max at t a = +25 c) shutdown state. during startup, the output voltage is ramped up at 1/4 the slew rate set by the time resistor to the boot voltage or to the target voltage. during the transition from normal operation to shutdown, the output voltage is ramped down at 1/6 the slew rate set by the time resistor. forcing shdn to 11v~13v to enter no-fault test mode clears the fault latches, disables transient phase overlap, and turns off the internal bst_-to-v dd switches. however, internal diodes still exist between bst_ and v dd in this state. deeper sleep vr control input. this low-voltage logic input indicates power usage and sets the operating mode together with psi as shown in the truth table below. when dprslpvr is forced high, the controller is immediately set to 1-phase automatic pulse-skipping mode. the controller returns to forced- pwm mode when dprslpvr is forced low and the output is in regulation. the pwrgd upper threshold is blanked during any downward output-voltage transition that happens when the controller is in skip mode, and stays blanked until the slew-rate-controlled internal-transition-related pwrgd blanking period is complete and the output reaches regulation. during this blanking period, the overvoltage fault threshold is changed from a tracking [vid + 300mv] threshold to a fixed 1.5v threshold. the controller is in n-phase skip mode during startup including boot mode, but is in n-phase forced-pwm mode during the transition from boot mode to vid mode, during soft-shutdown, irrespective of the dprslpvr and psi logic levels. however, if phases 2 and 3 are disabled by connecting csp2, csp3 to v cc , then only phase 1 is active in the above modes. dprslpvr psi mode 14 dprslpvr 1 0 0 x 0 1 very low current (1-phase skip) intermediate power potential (n-1-phase pwm) max power potential (full-phase pwm: n-phase or 1 phase as set by user at csp2, csp3)
MAX17030/max17036 1/2/3-phase quick-pwm imvp-6.5 vid controllers 14 ______________________________________________________________________________________ pin description (continued) pin name function this low-voltage logic input indicates power usage and sets the operating mode together with dprslpvr as shown in the truth table below. while dprslpvr is low, if psi is forced low, the controller is immediately set to (n-1)-phase forced-pwm mode. the controller returns to n-phase forced-pwm mode when psi is forced high. the controller is in n-phase skip mode during startup including boot mode, but is in n-phase forced-pwm mode during the transition from boot mode to vid mode, during soft-shutdown, irrespective of the dprslpvr and psi logic levels. however, if phases 2 and 3 are disabled by connecting csp2, csp3 to vcc, then only phase 1 is active in the above modes. dprslpvr psi mode 15 psi 1 0 0 x 0 1 very low current (1-phase skip) intermediate power potential (n-1-phase pwm) max power potential (full-phase pwm: n-phase or 1 phase as set by user at csp2, csp3) 16 ton switching frequency setting input. an external resistor between the input power source and this pin sets the switching frequency according to the following equation: f sw = 1/(c ton x (r ton + 6.5k )) where c ton = 16.26pf. the external resistor must also satisfy the requirement [v in(min) /r ton ] 10a where v in(min) is the minimum v in value expected in the application. ton is high impedance in shutdown. 17 clken clock enable cmos push-pull logic output powered by v 3p3 . this inverted logic output indicates when the output voltage sensed at fb is in regulation. clken is forced high in shutdown and during soft-start and soft-stop transitions. clken is forced low during dynamic vid transitions and for an additional 20s after the transition is completed. clken is the inverse of pwrgd, except for the 5ms pwrgd startup delay period after clken is pulled low. see the startup timing diagram (figure 9). the clken upper threshold is blanked during any downward output-voltage transition that happens when the controller is in skip mode, and stays blanked until the slew-rate-controlled internal-transition- related pwrgd blanking period is complete and the output reaches regulation. 18 pwrgd open-drain power-good output. after output-voltage transitions, except during power-up and power- down, if fb is in regulation, then pwrgd is high impedance. pwrgd is low during startup, continues to be low while the output is at the boot voltage, and stays low until 5ms (typ) after clken goes low, after which it starts monitoring the fb voltage and goes high if fb is within the pwrgd threshold window. pwrgd is forced low during soft-shutdown and while in shutdown. pwrgd is forced high impedance whenever the slew-rate controller is active (output-voltage transitions), and continues to be forced high impedance for an additional 20s after the transition is completed. the pwrgd upper threshold is blanked during any downward output-voltage transition that happens when the controller is in skip mode, and stays blanked until the slew-rate-controlled internal-transition-related pwrgd blanking period is complete and the output reaches regulation. a pullup resistor on pwrgd causes additional finite shutdown current. 19 drskp driver skip control output. push/pull logic output that controls the operating mode of the skip- mode driver ic. drskp swings from v dd to gnd. when drskp is high, the driver ics operate in forced-pwm mode. when drskp is low, the driver ics enable their zero-crossing comparators and operate in pulse-skipping mode. drskp goes low at the end of the soft-shutdown sequence, instructing the external drivers to shut down.
MAX17030/max17036 1/2/3-phase quick-pwm imvp-6.5 vid controllers ______________________________________________________________________________________ 15 pin description (continued) pin name function 20 pwm3 pwm signal output for phase 3. swings from gnd to v dd . three-state whenever phase 3 is disabled (in shutdown, when csp3 is connected to v cc , and when operating with fewer than all phases). 21 bst2 phase 2 boost flying capacitor connection. bst2 is the internal upper supply rail for the dh2 high- side gate driver. an internal switch between v dd and bst2 charges the bst2-lx2 flying capacitor while the low-side mosfet is on (dl2 pulled high). 22 lx2 phase 2 inductor connection. lx2 is the internal lower supply rail for the dh2 high-side gate driver. also used as an input to phase 2s zero-crossing comparator. 23 dh2 phase 2 high-side gate-driver output. dh2 swings from lx2 to bst2. low in shutdown. 24 dl2 phase 2 low-side gate-driver output. dl2 swings from gnd to v dd . dl2 is forced low in shutdown. dl2 is forced high when an output overvoltage fault is detected, overriding any negative current- limit condition that might be present. dl2 is forced low in skip mode after detecting an inductor current zero crossing. 25 vrhot open-drain output of internal comparator. vrhot is pulled low when the voltage at thrm goes below 1.5v (30% of v cc ). vrhot is high impedance in shutdown. 26 v dd supply voltage input for the dl_ drivers. v dd is also the supply voltage used to internally recharge the bst_-lx_ flying capacitor during the times the respective dl_s are high. connect v dd to the 4.5v to 5.5v system supply voltage. bypass v dd to gnd with a 1f or greater ceramic capacitor. 27 dl1 phase 1 low-side gate-driver output. dl1 swings from gnd to v dd . dl1 is forced low in shutdown. dl1 is forced high when an output overvoltage fault is detected, overriding any negative current- limit condition that might be present. dl1 is forced low in skip mode after detecting an inductor current zero crossing. 28 dh1 phase 1 high-side gate-driver output. dh1 swings from lx1 to bst1. low in shutdown. 29 lx1 phase 1 inductor connection. lx1 is the internal lower supply rail for the dh1 high-side gate driver. also used as an input to phase 1s zero-crossing comparator. 30 bst1 phase 1 boost flying capacitor connection. bst1 is the internal upper supply rail for the dh1 high- side gate driver. an internal switch between v dd and bst1 charges the bst1-lx1 flying capacitor while the low-side mosfet is on (dl1 pulled high). 31 pgd_in power-good logic input pin that indicates the power status of other system rails and used for supply sequencing. during startup, after soft-starting to the boot voltage, the output voltage remains at v boot , and the clken and pwrgd outputs remain high and low, respectively, as long as the pgd_in input stays low. when pgd_in later goes high, the output is allowed to transition to the voltage set by the vid code, and clken is allowed to go low. during normal operation, if pgd_in goes low, the controller immediately forces clken high and pwrgd low, and slews the output to the boot voltage while in skip mode at 1/4 the normal slew rate set by the time resistor. the output then stays at the boot voltage until the controller is turned off or power cycled, or until pgd_in goes high again. 32C38 d0Cd6 low-voltage (1.0v logic) vid dac code inputs. the d0Cd6 inputs do not have internal pullups. these 1.0v logic inputs are designed to interface directly with the cpu. the output voltage is set by the vid code indicated by the logic-level voltages on d0Cd6 (see table 4). the 1111111 code corresponds to a shutdown mode. when this code is detected, the MAX17030/max17036 initiate a soft-shutdown transition identical to the shutdown transition for a shdn falling edge. after slewing the output to 0v, it forces dh_, dl_, and drskp low, and three-states pwm3. the ic remains active and its v cc quiescent current consumption stays the same as in normal operation. if d6Cd0 is changed from 1111111 to a different code, the MAX17030/max17036 initiate a startup sequence identical to the startup sequence for a shdn rising edge. 39 csp1 positive input of the output current sense of phase 1. this pin should be connected to the positive side of the output current-sensing resistor or the filtering capacitor if the dc resistance of the output inductor is utilized for current sensing.
MAX17030/max17036 1/2/3-phase quick-pwm imvp-6.5 vid controllers 16 ______________________________________________________________________________________ pin description (continued) pin name function 40 csn1 negative input of the output current sense of phase 1. this pin should be connected to the negative side of the output current-sensing resistor or the filtering capacitor if the dc resistance of the output inductor is utilized for current sensing. a 10 discharge fet is turned on in uvlo event or thermal shutdown, or at the end of soft-shutdown. pad (gnd) exposed backplate (pad) of package. internally connected to both analog ground and power (driver) grounds. connect to the ground plane through a thermally enhanced via. max8791 c bst r2 2 ? r ntc1 r ilim1 r ilim2 r ton 200k ? ton bst1 c in n h shdn dprslpvr pgdin psi dprslpvr pgdin psi v dd 5v bias v cc 32 16 30 28 29 27 39 40 21 23 22 24 12 11 20 19 2 1 9 8 10 33 34 35 36 37 38 13 14 31 15 26 7 5 6 18 25 17 4 3 d1 d0 d2 d3 d4 d5 d6 8v to 20v pwr input output (imvp-6.5 core) on off (vron) pwrgd v cc v ccp v ss_sense vid inputs dh1 lx1 n l dl1 l1 r1 r catchgnd 10 ? csn1 c cs1 csp1 c out ilim time r thrm 13k ? thrm r pwrgd 1.9k ? r clken 1.9k ? r vrhot 56 ? vrhot clken r fb r fbs 10 ? r catchcore 10 ? r gnds 10 ? imon imon ntc 100k ? = 4250 pad r imon fb fbac gnds c fbs 1000pf c gnds 4700pf cpu remote sense 3.3v r vcc 20 ? c vdd 2.2 f c vcc 1.0 f c bst r5 r ntc2 bst2 c in n h 8v to 20v pwr input dh2 lx2 n l dl2 l2 r4 csn2 c cs2 csp2 c out c bst r8 r ntc3 bst c in n h 8v to 20v pwr input 5v bias dh lx n l dl l3 r7 csn3 c cs3 csp3 c out gnd v cc c vcc1 1.0 f pwm3 drskp pwm skip MAX17030 max17036 r3 r6 2 ? r9 2 ? v ss_sense v cc_sense figure 1. standard 3-phase imvp-6.5 application circuit
MAX17030/max17036 1/2/3-phase quick-pwm imvp-6.5 vid controllers ______________________________________________________________________________________ 17 design parameters imvp-6.5 xe core 3-phase imvp-6.5 sv core 3-phase imvp-6.5 sv core 2-phase circuit figure 1 figure 1 figure 2 input voltage range 8v to 20v 8v to 20v 8v to 20v maximum load current 65a (48a tdc) 52a (38a tdc) 52a (38a tdc) transient load current 49a (100a/s) 39a (100a/s) 39a (100a/s) load line -1.9mv/a -1.9mv/a -1.9mv/a poc setting 110 101 101 ton resistance (r ton ) 200k (f sw = 300khz) 200k (f sw = 300khz) 200k (f sw = 300khz) inductance (l) 0.36h, 36a, 0.82m (10mm x 10mm) panasonic etqp4lr36zfc 0.42h, 20a, 1.55m (7mm x 7mm) nec/tokin mpc0740lr42c 0.36h, 36a, 0.82m (10mm x 10mm) panasonic etqp4lr36zfc high-side mosfet (n h ) fairchildsemi 1x fds6298 9.4m /12m (typ/max) toshiba 1x tpca8030-h 9.6m /13.4m (typ/max) fairchildsemi 1x fds6298 9.4m /12m (typ/max) toshiba 1x tpca8030-h 9.6m /13.4m (typ/max fairchildsemi 1x fds6298 9.4m /12m (typ/max) toshiba 1x tpca8030-h 9.6m /13.4m (typ/max) low-side mosfet (n l ) fairchildsemi 2x fds8670 4.2m /5m (typ/max) toshiba 2x tpca8019-h fairchildsemi 1x fds8670 4.2m /5m (typ/max) toshiba 1x tpca8019-h fairchildsemi 2x fds8670 4.2m /5m (typ/max) toshiba 2x tpca8019-h output capacitors (c out ) (MAX17030 only) contact maxim for max17036 reference design 4x 330f, 2v, 4.5m panasonic eefsxod331e4 or nec/tokin psgvoe337m4.5 27x 22f, 6.3v x5r ceramic capacitor (0805) 3x 330f, 2v, 4.5m panasonic eefsxod331e4 or nec/tokin psgvoe337m4.5 27x 22f, 6.3v x5r ceramic capacitor (0805) 4x 330f, 6m , 2.5v panasonic eefsx0d0d331xr 28x 10f, 6v ceramic (0805) input capacitors (c in ) 6x 10f 25v ceramic (1210) 4x 10f 25v ceramic (1210) 4x 10f 25v ceramic (1210) time-ilim resistance (r ilim2 ) 14k 14k 16.9k ilim-gnd resistance (r ilim1 ) 137k 137k 133k fb resistance (r fb ) 6.04k 453k 6.04k imon resistance (r imon ) 12.1k 10.2k 14k lx-csp resistance 2.21k (r1, r4, r7) 1.4k (r1, r4, r7) 2.21k (r1, r7) csp-csn resistance 3.24k (r2, r5, r8) 40.2k (r3, r6, r9) 2k (r2, r5, r8) 40.2k (r3, r6, r9) 3.24k (r2, r8) 40.2k (r3, r9) dcr sense ntc (r ntc ) 10k ntc b = 3380 tdk ntcg163jh103f 10k ntc b = 3380 tdk ntcg163jh103f 10k ntc b = 3380 tdk ntcg163jh103f dcr sense capacitance (c sense ) 0.22f, 6v ceramic (0805) 0.22f, 6v ceramic (0805) 0.22f, 6v ceramic (0805) table 1. component selection for standard applications
MAX17030/max17036 1/2/3-phase quick-pwm imvp-6.5 vid controllers 18 ______________________________________________________________________________________ manufacturer website avx corp. www.avxcorp.com fairchild semiconductor www.fairchildsemi.com nec/tokin america, inc. www.nec-tokinamerica.com panasonic corp. www.panasonic.com sanyo electric co., ltd. www.sanyodevice.com manufacturer website siliconix (vishay) www.vishay.com taiyo yuden www.t-yuden.com tdk corp. www.component.tdk.com toko america, inc. www.tokoam.com toshiba america electronic components, inc. www.toshiba.com/taec table 2. component suppliers MAX17030 max17036 c bst r2 r ntc1 r ilim1 r ilim2 r ton 200k ? ton bst1 c in n h shdn dprslpvr pgdin psi dprslpvr pgdin psi v dd 5v bias v cc d0 d1 d2 d3 d4 d5 d6 8v to 20v pwr input output (imvp-6.5 core) on off (vron) pwrgd v cc v ccp vid inputs dh1 lx1 n l dl1 l1 r1 r catchgnd 10 ? csn1 c cs1 csp1 c out ilim time r thrm 13k ? thrm r pwrgd 1.9k ? r clken 1.9k ? r vrhot 56 ? vrhot clken r fb r fbs 10 ? r catchcore 10 ? r gnds 10 ? imon imon v ss_sense ntc 100k ? = 4250 pad r imon fb fbac gnds c fbs 1000pf cpu remote sense 3.3v r vcc 20 ? c vdd 2.2 f c vcc 1.0 f c bst r8 r ntc3 bst2 c in n h 8v to 20v pwr input 5v bias dh2 lx2 n l dl2 l2 r7 csn2 c cs2 csp2 c out csn3 csp3 pwm3 drskp 32 33 34 35 36 37 38 13 14 31 15 26 7 5 6 18 25 17 4 3 16 30 28 29 27 39 40 21 23 22 24 12 19 20 11 2 9 1 8 10 r3 2 ? 2 ? r9 v cc_sense v ss_sense figure 2. standard 2-phase imvp-6.5 application circuit
MAX17030/max17036 1/2/3-phase quick-pwm imvp-6.5 vid controllers ______________________________________________________________________________________ 19 thrm 0.3 x v cc vrhot csn3 csp3 10x csn2 csp2 10x csn1 ilim time v cc csp1 10x ref (2.0v) gnd d0?d6 dac r-to-i converter fault shdn pgdin target sel phase fb gnds fbac csn csp g m(fb) x3 MAX17030 max17036 pwm3 drskp one-shot phase 3 on-time q trig3 ton cc13 cc12 trig phase 3 driver control csp1 csn1 g m(cci) csn3 csp3 g m(cci) csp1 csn1 g m(cci) csn2 csp2 g m(cci) bst2 dh2 lx2 dl2 gnd one-shot phase 2 on-time q trig phase 2 drivers slew minimum off-time one shot q trig trig 3 s r q pgnd1 phase 1 on-time one-shot lx1 0mv r s q q trig skip dl1 pwrgd gnd v dd bst1 ton fb main phase drivers dh1 lx1 skip blank target + 200mv target - 300mv pgdin dprslpvr psi clken imon 60 s mode/phase/slew- rate control 5ms startup delay csp csn g m(imon) x3 figure 3. functional diagram
MAX17030/max17036 1/2/3-phase quick-pwm imvp-6.5 vid controllers 20 ______________________________________________________________________________________ detailed description free-running, constant-on-time pwm controller with input feed-forward the quick-pwm control architecture is a pseudo-fixed- frequency, constant-on-time, current-mode regulator with voltage feed-forward (figure 3). this architecture relies on the output filter capacitors esr to act as the current- sense resistor, so the output ripple voltage provides the pwm ramp signal. the control algorithm is simple: the high-side switch on-time is determined solely by a one- shot whose period is inversely proportional to input volt- age, and directly proportional to output voltage or the difference between the main and secondary inductor cur- rents (see the on-time one-shot section ) . another one- shot sets a minimum off-time. the on-time one-shot triggers when the error comparator goes low, the inductor current of the selected phase is below the valley current- limit threshold, and the minimum off-time one-shot times out. the controller maintains 120 out-of-phase operation by alternately triggering the three phases after the error comparator drops below the output-voltage set point. triple 120 out-of-phase operation the three phases in the MAX17030/max17036 operate 120 out-of-phase to minimize input and output filtering requirements, reduce electromagnetic interference (emi), and improve efficiency. this effectively lowers component countreducing cost, board space, and component power requirementsmaking the MAX17030/max17036 ideal for high-power, cost-sensitive applications. the MAX17030/max17036 share the current between three phases that operate 120 out-of-phase, so the high-side mosfets never turn on simultaneously dur- ing normal operation. the instantaneous input current of each phase is effectively reduced, resulting in reduced input voltage ripple, esr power loss, and rms ripple current (see the input capacitor selection sec- tion). therefore, the same performance can be achieved with fewer or less-expensive input capacitors. +5v bias supply (v cc and v dd ) the quick-pwm controller requires an external +5v bias supply in addition to the battery. typically, this +5v bias supply is the notebooks 95% efficient +5v system supply. the +5v bias supply must provide v cc (pwm controller) and v dd (gate-drive power), so the maximum current drawn is: where i cc is provided in the electrical characteristics table, f sw is the switching frequency, and q g(low) and q g(high) are the mosfet data sheets total gate- charge specification limits at v gs = 5v. v in and v dd can be connected together if the input power source is a fixed +4.5v to +5.5v supply. if the +5v bias supply is powered up prior to the battery sup- ply, the enable signal ( shdn going from low to high) must be delayed until the battery voltage is present to ensure startup. switching frequency (ton) connect a resistor (r ton ) between ton and v in to set the switching period t sw = 1/f sw , per phase: t sw = 16.26pf x (r ton + 6.5k ? ) a 96.75k ? to 303.25k ? corresponds to switching peri- ods of 167ns (600khz) to 500ns (200khz), respectively. high-frequency (600khz) operation optimizes the appli- cation for the smallest component size, trading off effi- ciency due to higher switching losses. low-frequency (200khz) operation offers the best overall efficiency at the expense of component size and board space. ton open-circuit protection the ton input includes open-circuit protection to avoid long, uncontrolled on-times that could result in an over- voltage condition on the output. the MAX17030/ max17036 detect an open-circuit fault if the ton current drops below 10a for any reasonthe ton resistor (r ton ) is unpopulated, a high resistance value is used, the input voltage is low, etc. under these conditions, the MAX17030/max17036 stop switching (dh and dl pulled low) and immediately set the fault latch. toggle shdn or cycle the v cc power supply below 0.5v to clear the fault latch and reactivate the controller. on-time one-shot the MAX17030/max17036 contain a fast, low-jitter, adjustable one-shot that sets the high-side mosfets on-time. it is shared among the three phases. the one- shot for the main phase varies the on-time in response to the input and feedback voltages. the main high-side switch on-time is inversely proportional to the input volt- age as measured by the v+ input, and proportional to the feedback voltage (v fb ): the one-shot for the second phase and third phase varies the on-time in response to the input voltage and the difference between the main and the other inductor currents. two identical transconductance amplifiers integrate the difference between the master and each slaves current-sense signals. the summed output is connected to an internal integrator for each master- slave pair, which serves as the input to the respective slaves high-side mosfet ton timer. t tv v v on sw fb in = + () 0 075 . iifq q bias cc sw g low g high =+ + () () ( )
MAX17030/max17036 1/2/3-phase quick-pwm imvp-6.5 vid controllers ______________________________________________________________________________________ 21 when the main and other phase current-sense signals (v cm = v cmp - v cmn and v cs = v csp - v csm ) become unbalanced, the transconductance amplifiers adjust the other phases on-time, which increases or decreases the phase inductor current until the current-sense sig- nals are properly balanced: where v cci is the internal integrator node for each slaves current-balance integrator, and z cci is the effective impedance at that node. during phase overlap, t on is calculated based on phase 1s on-time requirements, but reduced by 33% when operating with three phases. for a 3-phase regulator, each phase cannot be enabled until the other 2 phases have completed their on-time and the minimum off-times have expired. as such, the minimum period is limited by 3 x (t on + t off(min) ). maximum t on is dependent on minimum v in and maximum output voltage: t sw(min) = n ph x (t on(max) + t off(min) ) where: t on(max) = v fb(max) /v in(min x t sw(min) so: t sw(min) = t off(min) /[1/n ph C v in(max) /v in(min) ] hence, for a 7v input and 1.1v output, 500khz is the maximum switching frequency. running at this limit is not desirable as there is no room to allow the regulator to make adjustments without triggering phase overlap. for a 3-phase, high-current application with minimum 8v input, the practical switching frequency is 300khz. on-times translate only roughly to switching frequen- cies. the on-times guaranteed in the electrical characteristics are influenced by parasitics in the con- duction paths and propagation delays. for loads above the critical conduction point, where the dead-time effect (lx flying high and conducting through the high-side fet body diode) is no longer a factor, the actual switching frequency (per phase) is: where v dis and v chg are the sum of the parasitic volt- age drops in the inductor discharge and charge paths, including mosfet, inductor, and pcb resistances; v chg is the sum of the parasitic voltage drops in the inductor charge path, including high-side switch, inductor, and pcb resistances; and t on is the on-time as determined above. current sense the MAX17030/max17036 sense the output current of each phase allowing the use of current-sense resistors on inductor dcr as the current-sense element. low- offset amplifiers are used for current balance, voltage- positioning gain, and current limit. using the dc resistance (r dcr ) of the output inductor allows higher efficiency. the initial tolerance and tem- perature coefficient of the inductors dcr must be accounted for in the output-voltage droop-error budget and current monitor. this current-sense method uses an rc filtering network to extract the current information from the output inductor (see figure 4). the rc network should match the inductors time constant (l/r dcr ): and: where r cs is the required current-sense resistance, and r dcr is the inductors series dc resistance. use the typical inductance and r dcr values provided by the inductor manufacturer. to minimize the current- sense error due to the current-sense inputs bias current (i csp_ and i csn_ ), choose r1//r2 to be less than 2k ? and use the above equation to determine the sense capacitance (c eq ). choose capacitors with 5% toler- ance and resistors with 1% tolerance specifications. temperature compensation is recommended for this current-sense method. see the voltage positioning and loop compensation section for detailed information. when using a current-sense resistor for accurate out- put-voltage positioning, the circuit requires a differential rc filter to eliminate the ac voltage step caused by the equivalent series inductance (l esl ) of the current- sense resistor (see figure 4). the esl induced voltage step might affect the average current-sense voltage. the rc filters time constant should match the l esl / r sense time constant formed by the current-sense resistors parasitic inductance: l r cr esl sense eq eq = r l crr cs eq =+ ? ? ? ? ? ? 1 1 1 2 r r rr r cs dcr = + ? ? ? ? ? ? 2 12 f vv tvv v sw out dis on in dis chg = + () +? () tt vv v t v on sec sw cci in sw fb () . . = + ? ? ? ? ? ? = + 0 075 00 7 75v v t iz v in sw cci cci in ? ? ? ? ? ? + ? ? ? ? ? ? = main on-t time secondary current balance correctio () + n n ()
MAX17030/max17036 1/2/3-phase quick-pwm imvp-6.5 vid controllers 22 ______________________________________________________________________________________ where l esl is the equivalent series inductance of the cur- rent-sense resistor, r sense is current-sense resistance value, and c eq and r eq are the time-constant matching components. current balance the MAX17030/max17036 integrate the difference between the current-sense voltages and adjust the on- time of the secondary phase to maintain current bal- ance. the current balance relies on the accuracy of the current-sense signals across the current-sense resistor or inductor dcr. with active current balancing, the cur- rent mismatch is determined by the current-sense resis- tor or inductor dcr values and the offset voltage of the transconductance amplifiers: where r sense = r cm = r cs and v os(ibal) is the current balance offset specification in the electrical characteristics table. the worst-case current mismatch occurs immediately after a load transient due to inductor value mismatches resulting in different di/dt for the two phases. the time it takes the current-balance loop to correct the transient imbalance depends on the mismatch between the inductor values and switching frequency. iii v r os ibal lmain lsec os ibal sense () () =?= a) output series resistor sensing dh_ input (v in ) dl_ lx_ c in n l n h d l csp_ csn_ l b) lossless inductor sensing dh_ input (v in ) dl_ lx_ c in n l n h d l csp_ csn_ c out inductor r1 c eq l r dcr sense resistor l esl r sense c out r eq c eq r2 r sense l esl c eq r eq = r dcr r1 + r2 r2 r cs = 1 1 r1 r2 c eq l r dcr = [ + ] for thermal compensation: r2 should consist of an ntc resistor in series with a standard thin-film resistor MAX17030 max17036 MAX17030 max17036 figure 4. current-sense methods
MAX17030/max17036 1/2/3-phase quick-pwm imvp-6.5 vid controllers ______________________________________________________________________________________ 23 current limit the current-limit circuit employs a unique valley cur- rent-sensing algorithm that senses the voltage across the current-sense resistors or inductor dcr at the cur- rent-sense inputs (csp_ to csn_). if the current-sense signal of the selected phase is above the current-limit threshold, the pwm controller does not initiate a new cycle until the inductor current of the selected phase drops below the valley current-limit threshold. when any one phase exceeds the current limit, all phases are effectively current limited since the interleaved con- troller does not initiate a cycle with the next phase. since only the valley current is actively limited, the actu- al peak current is greater than the current-limit thresh- old by an amount equal to the inductor ripple current. therefore, the exact current-limit characteristic and maximum load capability are a function of the current- sense resistance, inductor value, and battery voltage. the positive valley current-limit threshold voltage at csp to csn equals precisely 1/10 of the differential time to ilim voltage over a 0.1v to 0.5v range (10mv to 50mv current-sense range). connect ilim directly to v cc to set the default current-limit threshold setting of 22.5mv (typ). the negative current-limit threshold (forced-pwm mode only) is nominally -125% of the corresponding valley current-limit threshold. when the inductor current drops below the negative current limit, the controller immedi- ately activates an on-time pulsedl turns off, and dh turns onallowing the inductor current to remain above the negative current threshold. carefully observe the pcb layout guidelines to ensure that noise and dc errors do not corrupt the current-sense signals seen by the current-sense inputs (csp_, csn_). feedback adjustment amplifiers voltage-positioning amplifier (steady-state droop) the MAX17030/max17036 include a transconductance amplifier for adding gain to the voltage-positioning sense path. the amplifiers input is generated by summing the current-sense inputs, which differentially sense the volt- age across either current-sense resistors or the induc- tors dcr. the amplifiers output connects directly to the regulators voltage-positioned feedback input (fb), so the resistance between fb and the output-voltage sense point determines the voltage-positioning gain: where the target voltage (v target ) is defined in the nominal output voltage selection section, and the fb amplifiers output current (i fb ) is determined by the sum of the current-sense voltages: where v csx = v csp - v csn is the differential current- sense voltage, and g m(fb) is typically 400s as defined in the electrical characteristics . differential remote sense the MAX17030/max17036 include differential, remote- sense inputs to eliminate the effects of voltage drops along the pcb traces and through the processors power pins. the feedback-sense node connects to the voltage-positioning resistor (r fb ). the ground-sense (gnds) input connects to an amplifier that adds an off- set directly to the target voltage, effectively adjusting the output voltage to counteract the voltage drop in the ground path. connect the voltage-positioning resistor (r fb ) and ground sense (gnds) input directly to the processors remote sense outputs as shown in figure 1. integrator amplifier an internal integrator amplifier forces the dc average of the fb voltage to equal the target voltage, allowing accurate dc output-voltage regulation regardless of the output ripple voltage. the MAX17030/max17036 disable the integrator by connecting the amplifier inputs together at the begin- ning of all vid transitions done in pulse-skipping mode (dprslpvr = high). the integrator remains disabled until 20s after the transition is completed (the internal target settles) and the output is in regulation (edge detected on the error comparator). transient overlap operation when a transient occurs, the response time of the con- troller depends on how quickly it can slew the inductor current. multiphase controllers that remain 120 out-of- phase when a transient occurs actually respond slower than an equivalent single-phase controller. in order to provide fast transient response, the MAX17030/ max17036 support a phase overlap mode, which allows the triple regulators to operate in-phase when heavy load transients are detected, effectively reducing the response time. after any high-side mosfet turns off, if the output voltage does not exceed the regulation voltage when the minimum off-time expires, the con- troller simultaneously turns on all high-side mosfets with the same on-time during the next on-time cycle. the phases remain overlapped until the output voltage exceeds the regulation voltage after the minimum ig v fb m fb csx x ph = = () 1 vv ri out target fb fb =?
MAX17030/max17036 1/2/3-phase quick-pwm imvp-6.5 vid controllers 24 ______________________________________________________________________________________ * multiphase operation = all enabled phases active. off-time expires. the on-time for each phase is based on the input voltage to fb ratio (i.e., follows the master on-time), but reduced by 33% in a 3-phase configura- tion, and not reduced in a 2-phase configuration. this maximizes the total inductor current slew rate. after the phase-overlap mode ends, the controller auto- matically begins with the next phase. for example, if phase 2 provided the last on-time pulse before overlap operation began, the controller starts switching with phase 3 when overlap operation ends. nominal output voltage selection the nominal no-load output voltage (v target ) is defined by the selected voltage reference (vid dac) plus the remote ground-sense adjustment (v gnds ) as defined in the following equation: where v dac is the selected vid voltage. on startup, the MAX17030/max17036 slew the target voltage from ground to the preset boot voltage. table 3 is the operating mode truth table. dac inputs (d0?6) the digital-to-analog converter (dac) programs the out- put voltage using the d0Cd6 inputs. d0Cd6 are low-volt- age (1.0v) logic inputs, designed to interface directly with the cpu. do not leave d0Cd6 unconnected. changing d0Cd6 initiates a transition to a new output-voltage level. change d0Cd6 together, avoiding greater than 20ns skew between bits. otherwise, incorrect dac readings might cause a partial transition to the wrong voltage level followed by the intended transition to the correct voltage level, lengthening the overall transition time. the available dac codes and resulting output voltages are compatible with the imvp-6.5 (table 4) specifications. off code vid = 1111111 is defined as an off code. when the off code is set, the MAX17030/max17036 go through the same shutdown sequence as though shdn has been pulled lowoutput discharged to zero, clken high, and pwrgd low. only the ic supply currents remain at the operating levels rather than the shutdown level. when exiting from the off code, the MAX17030/ max17036 go through the boot sequence, similar to the sequence when shdn is first pulled high. vvvv target fb dac gnds == + inputs shdn dprslpvr psi phase operation* operating mode gnd x x disabled low-power shutdown mode. dl1 and dl2 forced low, and the controller is disabled. the supply current drops to 1a (max). rising x x multiphase pulse skipping 1/4 r time slew rate startup/boot. when shdn is pulled high, the MAX17030/ max17036 begin the startup sequence. once the ref is above 1.84v, the controller enables the pwm controller and ramps the output voltage up to the boot voltage. see figure 9. high low high multiphase forced-pwm nominal r time slew rate full power. the no-load output voltage is determined by the selected vid dac code (d0Cd6, table 4). high low low (n-1)-phase forced-pwm nominal r time slew rate intermediate power. the no-load output voltage is determined by the selected vid dac code (d0Cd6, table 4). when psi is pulled low, the MAX17030/max17036 immediately disable phase 3, pwm3 is three-state, and drskp is low. high high x 1-phase pulse skipping nominal r time slew rate deeper sleep mode. the no-load output voltage is determined by the selected vid dac code (d0Cd6, table 4). when dprslpvr is pulled high, the MAX17030/max17036 immediately enter 1-phase pulse- skipping operation allowing automatic pwm/pfm switchover under light loads. the pwrgd and clken upper thresholds are blanked. dh2 and dl2 are pulled low, pwm3 is three-state and drskp is low. table 3. operating mode truth table
MAX17030/max17036 1/2/3-phase quick-pwm imvp-6.5 vid controllers ______________________________________________________________________________________ 25 inputs shdn dprslpvr psi phase operation* operating mode falling x x multiphase forced-pwm 1/4 r time slew rate shutdown. when shdn is pulled low, the MAX17030/max17036 immediately pull pwrgd low, clken becomes high impedance, all enabled phases are activated, and the output voltage is ramped down to 12.5mv; then dh and dl are pulled low and csni discharge fet is turned on. high x x disabled fault mode. the fault latch has been set by the MAX17030/max17036 uvp or thermal-shutdown protection, or by the ovp protection. the controller remains in fault mode until v cc power is cycled or shdn toggled. table 3. operating mode truth table (continued) * multiphase operation = all enabled phases active. d6 d5 d4 d3 d2 d1 d0 output voltage (v) d6 d5 d4 d3 d2 d1 d0 output voltage (v) 0 0 0 0 0 0 0 1.5000 1 0 0 0 0 0 0 0.7000 0 0 0 0 0 0 1 1.4875 1 0 0 0 0 0 1 0.6875 0 0 0 0 0 1 0 1.4750 1 0 0 0 0 1 0 0.6750 0 0 0 0 0 1 1 1.4625 1 0 0 0 0 1 1 0.6625 0 0 0 0 1 0 0 1.4500 1 0 0 0 1 0 0 0.6500 0 0 0 0 1 0 1 1.4375 1 0 0 0 1 0 1 0.6375 0 0 0 0 1 1 0 1.4250 1 0 0 0 1 1 0 0.6250 0 0 0 0 1 1 1 1.4125 1 0 0 0 1 1 1 0.6125 0 0 0 1 0 0 0 1.4000 1 0 0 1 0 0 0 0.6000 0 0 0 1 0 0 1 1.3875 1 0 0 1 0 0 1 0.5875 0 0 0 1 0 1 0 1.3750 1 0 0 1 0 1 0 0.5750 0 0 0 1 0 1 1 1.3625 1 0 0 1 0 1 1 0.5625 0 0 0 1 1 0 0 1.3500 1 0 0 1 1 0 0 0.5500 0 0 0 1 1 0 1 1.3375 1 0 0 1 1 0 1 0.5375 0 0 0 1 1 1 0 1.3250 1 0 0 1 1 1 0 0.5250 0 0 0 1 1 1 1 1.3125 1 0 0 1 1 1 1 0.5125 0 0 1 0 0 0 0 1.3000 1 0 1 0 0 0 0 0.5000 0 0 1 0 0 0 1 1.2875 1 0 1 0 0 0 1 0.4875 0 0 1 0 0 1 0 1.2750 1 0 1 0 0 1 0 0.4750 0 0 1 0 0 1 1 1.2625 1 0 1 0 0 1 1 0.4625 0 0 1 0 1 0 0 1.2500 1 0 1 0 1 0 0 0.4500 0 0 1 0 1 0 1 1.2375 1 0 1 0 1 0 1 0.4375 0 0 1 0 1 1 0 1.2250 1 0 1 0 1 1 0 0.4250 0 0 1 0 1 1 1 1.2125 1 0 1 0 1 1 1 0.4125 0 0 1 1 0 0 0 1.2000 1 0 1 1 0 0 0 0.4000 0 0 1 1 0 0 1 1.1875 1 0 1 1 0 0 1 0.3875 table 4. imvp-6.5 output voltage vid dac codes
MAX17030/max17036 1/2/3-phase quick-pwm imvp-6.5 vid controllers 26 ______________________________________________________________________________________ d6 d5 d4 d3 d2 d1 d0 output voltage (v) d6 d5 d4 d3 d2 d1 d0 output voltage (v) 0 0 1 1 0 1 0 1.1750 1 0 1 1 0 1 0 0.3750 0 0 1 1 0 1 1 1.1625 1 0 1 1 0 1 1 0.3625 0 0 1 1 1 0 0 1.1500 1 0 1 1 1 0 0 0.3500 0 0 1 1 1 0 1 1.1375 1 0 1 1 1 0 1 0.3375 0 0 1 1 1 1 0 1.1250 1 0 1 1 1 1 0 0.3250 0 0 1 1 1 1 1 1.1125 1 0 1 1 1 1 1 0.3125 0 1 0 0 0 0 0 1.1000 1 1 0 0 0 0 0 0.3000 0 1 0 0 0 0 1 1.0875 1 1 0 0 0 0 1 0.2875 0 1 0 0 0 1 0 1.0750 1 1 0 0 0 1 0 0.2750 0 1 0 0 0 1 1 1.0625 1 1 0 0 0 1 1 0.2625 0 1 0 0 1 0 0 1.0500 1 1 0 0 1 0 0 0.2500 0 1 0 0 1 0 1 1.0375 1 1 0 0 1 0 1 0.2375 0 1 0 0 1 1 0 1.0250 1 1 0 0 1 1 0 0.2250 0 1 0 0 1 1 1 1.0125 1 1 0 0 1 1 1 0.2125 0 1 0 1 0 0 0 1.0000 1 1 0 1 0 0 0 0.2000 0 1 0 1 0 0 1 0.9875 1 1 0 1 0 0 1 0.1875 0 1 0 1 0 1 0 0.9750 1 1 0 1 0 1 0 0.1750 0 1 0 1 0 1 1 0.9625 1 1 0 1 0 1 1 0.1625 0 1 0 1 1 0 0 0.9500 1 1 0 1 1 0 0 0.1500 0 1 0 1 1 0 1 0.9375 1 1 0 1 1 0 1 0.1375 0 1 0 1 1 1 0 0.9250 1 1 0 1 1 1 0 0.1250 0 1 0 1 1 1 1 0.9125 1 1 0 1 1 1 1 0.1125 0 1 1 0 0 0 0 0.9000 1 1 1 0 0 0 0 0.1000 0 1 1 0 0 0 1 0.8875 1 1 1 0 0 0 1 0.0875 0 1 1 0 0 1 0 0.8750 1 1 1 0 0 1 0 0.0750 0 1 1 0 0 1 1 0.8625 1 1 1 0 0 1 1 0.0625 0 1 1 0 1 0 0 0.8500 1 1 1 0 1 0 0 0.0500 0 1 1 0 1 0 1 0.8375 1 1 1 0 1 0 1 0.0375 0 1 1 0 1 1 0 0.8250 1 1 1 0 1 1 0 0.0250 0 1 1 0 1 1 1 0.8125 1 1 1 0 1 1 1 0.0125 0 1 1 1 0 0 0 0.8000 1 1 1 1 0 0 0 0 0 1 1 1 0 0 1 0.7875 1 1 1 1 0 0 1 0 0 1 1 1 0 1 0 0.7750 1 1 1 1 0 1 0 0 0 1 1 1 0 1 1 0.7625 1 1 1 1 0 1 1 0 0 1 1 1 1 0 0 0.7500 1 1 1 1 1 0 0 0 0 1 1 1 1 0 1 0.7375 1 1 1 1 1 0 1 0 0 1 1 1 1 1 0 0.7250 1 1 1 1 1 1 0 0 0 1 1 1 1 1 1 0.7125 1 1 1 1 1 1 1 off table 4. imvp-6.5 output voltage vid dac codes (continued)
MAX17030/max17036 1/2/3-phase quick-pwm imvp-6.5 vid controllers ______________________________________________________________________________________ 27 suspend mode when the processor enters low-power deeper sleep mode, the imvp-6.5 cpu sets the vid dac code to a lower output voltage and drives dprslpvr high. the MAX17030/max17036 respond by slewing the internal target voltage to the new dac code, switching to single- phase operation, and letting the output voltage gradual- ly drift down to the deeper sleep voltage. during the transition, the MAX17030/max17036 blank both the upper and lower pwrgd and clken thresholds until 20s after the internal target reaches the deeper sleep voltage. once the 20s timer expires, the MAX17030/ max17036 reenable the lower pwrgd and clken threshold, but keep the upper threshold blanked. output-voltage-transition timing at the beginning of an output-voltage transition, the MAX17030/max17036 blank both pwrgd thresholds, preventing the pwrgd open-drain output from chang- ing states during the transition. the controller enables the lower pwrgd threshold approximately 20s after the slew-rate controller reaches the target output volt- age, but the upper pwrgd threshold is enabled only if the controller remains in forced-pwm operation. if the controller enters pulse-skipping operation, the upper pwrgd threshold remains blanked. the slew rate (set by resistor r time ) must be set fast enough to ensure that the transition can be completed within the maxi- mum allotted time. the MAX17030/max17036 automatically control the cur- rent to the minimum level required to complete the transi- tion. the total transition time depends on r time , the voltage difference, and the accuracy of the slew-rate controller (c slew accuracy). the slew rate is not depen- dent on the total output capacitance, as long as the surge current is less than the current limit. for all dynam- ic vid transitions, the transition time (t tran ) is given by: where dv target /dt = 12.5mv/s 71.5k ? /r time is the slew rate, v old is the original output voltage, and v new is the new target voltage. see time slew-rate accuracy in the electrical characteristics for slew-rate limits. for soft-start and shutdown, the controller auto- matically reduces the slew rate to 1/4. the average inductor current per phase required to make an output-voltage transition is: where dv target /dt is the required slew rate, c out is the total output capacitance, and total is the number of active phases. deeper sleep transitions when dprslpvr goes high, the MAX17030/max17036 immediately disable phases 2 and 3 (dh2, dl2 forced low, pwm3 three-state, drskp low), and enter pulse- skipping operation (see figures 5 and 6). if the vids are set to a lower voltage setting, the output drops at a rate determined by the load and the output capacitance. the internal target still ramps as before, and pwrgd remains blanked high impedance until 20s after the output voltage reaches the internal target. once this time expires, pwrgd monitors only the lower threshold: fast c4e deeper sleep exit: when exiting deeper sleep (dprslpvr pulled low) while the output volt- age still exceeds the deeper sleep voltage, the MAX17030/max17036 quickly slew (50mv/s min regardless of r time setting) the internal target volt- age to the dac code provided by the processor as long as the output voltage is above the new target. the controller remains in skip mode until the output voltage equals the internal target. once the internal target reaches the output voltage, phase 2 is enabled. the controller blanks pwrgd and clken (forced high impedance) until 20s after the transi- tion is completed. see figure 5. standard c4 deeper sleep exit: when exiting deeper sleep (dprslpvr pulled low) while the out- put voltage is regulating to the deeper sleep volt- age, the MAX17030/max17036 immediately activate all enabled phases and ramp the output voltage to the lfm dac code provided by the processor at the slew rate set by r time . the con- troller blanks pwrgd and clken (forced high impedance) until 20s after the transition is com- pleted. see figure 6. i c dv dt l out total target ? () t vv dv dt tran new old target = ? ()
MAX17030/max17036 1/2/3-phase quick-pwm imvp-6.5 vid controllers 28 ______________________________________________________________________________________ cpu core voltage internal pwm control vid (d0?d6) dprslpvr actual v out internal target deeper sleep vid blank high-z t blank 20 s typ t blank 20 s typ blank hi-z blank high threshold only blank low blank lo blank high threshold only set to 1.5v min tracks internal target do not care (dprslpvr dominates state) 1-phase skip (dh1 active, dh2, dl2 forced low, pwm3 three-state) no pulses: v out > v target forced-pwm ovp dh2 dh1 pwm3 pwrgd psi clken figure 5. c4e (c4 early exit) transition dprslpvr internal pwm control dh1 ovp cpu core voltage internal target actual v out psi vid (d0d6) active vid lfm vid dprslp vid dh2 pwm3 t blank 20 s typ t blank 20 s typ set to 1.5v min tracks internal target no pulses: v out > v target 1-phase skip (dh1 active, dh2, dl2 forced low, pwm3 three-state) do not care (dprslpvr dominates state) forced-pwm deeper sleep vid lfm vid pwrgd clken blank low blank high threshold only blank high threshold only blank high-z blank low blank high-z figure 6. standard c4 transition
MAX17030/max17036 1/2/3-phase quick-pwm imvp-6.5 vid controllers ______________________________________________________________________________________ 29 psi transitions when psi is pulled low, the MAX17030/max17036 immediately disable phase 3 (pwm3 three-state, drskp forced low) and enter 2-phase pwm operation (see figure 7). when psi is pulled high, the MAX17030/ max17036 enable phase 3. forced-pwm operation (normal mode) during soft-shutdown and normal operationwhen the cpu is actively running (dprslpvr = low, table 5) the MAX17030/max17036 operate with the low-noise, forced-pwm control scheme. forced-pwm operation disables the zero-crossing comparators of all active phases, forcing the low-side gate-drive waveforms to constantly be the complement of the high-side gate- drive waveforms. this keeps the switching frequency constant and allows the inductor current to reverse under light loads, providing fast, accurate negative out- put-voltage transitions by quickly discharging the output capacitors. forced-pwm operation comes at a cost: the no-load +5v bias supply current remains between 10ma to 50ma per phase, depending on the external mosfets and switching frequency. to maintain high efficiency under light-load conditions, the processor can switch the controller to a low-power pulse-skipping control scheme by entering suspend mode. psi determines how many phases are active when oper- ating in forced-pwm mode (dprslpvr = low). when psi is pulled low, phases 1 and 2 remain active but phase 3 is disabled (pwm3 three-state, drskp forced low). light-load pulse-skipping operation (deeper sleep) during soft-start and normal operation when dprslpvr is pulled high, the MAX17030/ max17036 operate with a single-phase pulse-skipping mode. the pulse-skipping mode enables the drivers zero-crossing comparator, so the controller pulls dl1 low when its cur- rent-sense inputs detect zero inductor current. this keeps the inductor from discharging the output capaci- tors and forces the controller to skip pulses under light- load conditions to avoid overcharging the output. cpu freq cpu load cpu core voltage vid (d0?d6) pwrgd pwm3 dh2 dh1 psi clken t blank 20 s typ t blank 20 s typ blank high-z pwm3 three-state 180 out-of-phase blank low blank high-z blank low figure 7. psi transition
MAX17030/max17036 1/2/3-phase quick-pwm imvp-6.5 vid controllers 30 ______________________________________________________________________________________ when pulse-skipping, the controller blanks the upper pwrgd and clken thresholds. upon entering pulse- skipping operation, the controller temporarily sets the ovp threshold to 1.5v, preventing false ovp faults when the transition to pulse-skipping operation coin- cides with a vid code change. once the error amplifier detects that the output voltage is in regulation, the ovp threshold tracks the selected vid dac code. the MAX17030/max17036 automatically use forced-pwm operation during soft-start and soft shutdown, regard- less of the dprslpvr and psi configuration. automatic pulse-skipping switchover in skip mode (dprslpvr = high), an inherent automatic switchover to pfm takes place at light loads (figure 8). this switchover is affected by a comparator that trun- cates the low-side switch on-time at the inductor cur- rents zero crossing. the zero-crossing comparator senses the inductor current across the low-side mosfets. once v lx drops below the zero-crossing comparator threshold (see the electrical characteristics ), the comparator forces dl low. this mechanism causes the threshold between pulse-skipping pfm and non- skipping pwm operation to coincide with the boundary between continuous and discontinuous inductor-current operation. the pfm/pwm crossover occurs when the load current of each phase is equal to 1/2 the peak-to- peak ripple current, which is a function of the inductor value (figure 8). for a battery input range of 7v to 20v, this threshold is relatively constant, with only a minor dependence on the input voltage due to the typically low duty cycles. the total load-current at the pfm/pwm crossover threshold (i load(skip) ) is approximately: power-up sequence (por, uvlo) the MAX17030/max17036 are enabled when shdn is driven high (figure 9). the reference powers up first. once the reference exceeds its undervoltage-lockout (uvlo) threshold, the internal analog blocks are turned on and masked by a 150s one-shot delay. the pwm controller then begins switching. i tv l vv v load skip sw out in out in () = ? ? ? ? ? ? ? ? ? ? - 2 ? ? ? i peak i load = i peak /2 inductor current time 0 l v in ? v out ? t ? i = on-time figure 8. pulse-skipping/discontinuous crossover point forced-pwm t blank 20 s typ t blank 60 s typ t blank 5ms typ t blank 20 s typ vid (d0?d6) v core imvpok internal pwm control v cc soft-start 1/4 slew rate set by r time shdn ignore vid ignore vid pulse-skipping clken soft-shutdown 1/4 slew rate set by r time figure 9. power-up and shutdown sequence timing diagram
MAX17030/max17036 1/2/3-phase quick-pwm imvp-6.5 vid controllers ______________________________________________________________________________________ 31 power-on reset (por) occurs when v cc rises above approximately 2v, resetting the fault latch and prepar- ing the controller for operation. the v cc uvlo circuitry inhibits switching until v cc rises above 4.25v. the con- troller powers up the reference once the system enables the controller, v cc is above 4.25v, and shdn driven high. with the reference in regulation, the con- troller ramps the output voltage to the boot voltage (1.1v) at 1/4 the slew rate set by r time : where dv target /dt = 12.5mv/s x 71.5k ? /r time is the slew rate. the soft-start circuitry does not use a variable current limit, so full output current is available immedi- ately. clken is pulled low approximately 60s after the MAX17030/max17036 reach the boot voltage. at the same time, the MAX17030/max17036 slew the output to the voltage set at the vid inputs at the programmed slew rate. pwrgd becomes high impedance approxi- mately 5ms after clken is pulled low. the MAX17030/ max17036 automatically operate in pulse-skipping mode during soft-start, and use forced-pwm operation during soft-shutdown, regardless of the dprslpvr and psi configuration. if the v cc voltage drops below 4.25v, the controller assumes that there is not enough supply voltage to make valid decisions, and shuts down immediately. dh and dl are forced low, and csni 10 ? discharge fet is enabled. shutdown when shdn goes low, the MAX17030/max17036 enters low-power shutdown mode. pwrgd is pulled low immediately, and the output voltage ramps down at 1/4 the slew rate set by r time : where dv target /dt = 12.5mv/s x 71.5k ? /r time is the slew rate. after the output voltage drops to 12.5mv, the MAX17030/max17036 shut down completelythe dri- vers are disabled (dl1 and dl2 driven low, pwm3 is three-state, and drskp low), the reference turns off, 10 ? csni discharge fet is turned on, and the supply current drops below 1a. when an undervoltage fault condition activates the shut- down sequence, the protection circuitry sets the fault latch to prevent the controller from restarting. to clear the fault latch and reactivate the controller, toggle shdn or cycle v cc power below 0.5v. current monitor (imon) the MAX17030/max17036 include a unidirectional transconductance amplifier that sources current pro- portional to the positive current-sense voltage. the imon output current is defined by: i imon = g m(imon) x (v csp - v csn ) where g m(imon) = 1.6ms (typ) and the imon current is unidirectional (sources current out of imon only) for positive current-sense values. for negative current- sense voltages, the imon current is zero. connect an external resistor between imon and gnds to create the desired imon gain based on the following equation: r imon = 0.9v/(i max x r sense(min) x g m(imon_min) ) where i max is defined in the current monitor section of the intel imvp-6.5 specification and based on discrete increments (10a, 20a, 30a, 40a, etc.), r sense(min) is the minimum effective value of the current-sense ele- ment (sense resistor or inductor dcr) that is used to provide the current-sense voltage, and g m(imon_min) is the minimum transconductance amplifier gain as defined in the electrical characteristics . the imon voltage is internally clamped to a maximum of 1.1v (typ), preventing the imon output from exceed- ing the imon voltage rating even under overload or short-circuit conditions. when the controller is disabled, imon is pulled to ground. the transconductance amplifier and voltage clamp are internally compensated, so imon cannot directly drive large capacitance values. to filter the imon signal, use an rc filter as shown in figure 1. temperature comparator ( vrhot ) the MAX17030/max17036 also feature an independent comparator with an accurate threshold (v hot ) that tracks the analog supply voltage (v hot = 0.3v cc ). this makes the thermal trip threshold independent of the v cc supply voltage tolerance. use a resistor- and thermistor- divider between v cc and gnd to generate a voltage- regulator overtemperature monitor. place the thermistor as close to the mosfets and inductors as possible. fault protection (latched) output overvoltage protection the overvoltage-protection (ovp) circuit is designed to protect the cpu against a shorted high-side mosfet by drawing high current and blowing the battery fuse. the MAX17030/max17036 continuously monitor the output for an overvoltage fault. an ovp fault is detected if the output voltage exceeds the set vid dac voltage by more than 300mv, or the fixed 1.5v (typ) threshold t v dv dt tran shdn out target () = () 4 t v dv dt tran start boot target () = () 4
MAX17030/max17036 1/2/3-phase quick-pwm imvp-6.5 vid controllers 32 ______________________________________________________________________________________ during a downward vid transition in skip mode. during pulse-skipping operation (dprslpvr = high), the ovp threshold tracks the vid dac voltage as soon as the output is in regulation; otherwise, the fixed 1.5v (typ) threshold is used. when the ovp circuit detects an overvoltage fault while in multiphase mode (dprslpvr = low, psi = high), the MAX17030/max17036 immediately force dl1 and dl2 high, pwm3 low, and drskp high; and pull dh1 and dh2 low. this action turns on the synchronous-rectifier mosfets with 100% duty and, in turn, rapidly dis- charges the output filter capacitor and forces the output low. if the condition that caused the overvoltage (such as a shorted high-side mosfet) persists, the battery fuse blows. toggle shdn or cycle the v cc power supply below 0.5v to clear the fault latch and reactivate the con- troller. when an overvoltage fault occurs while in 1-phase operation (dprslpvr = high, or psi = low), the MAX17030/max17036 immediately force dl1 high and pull dh1 low. dl2 and dh2 remain low as phase 2 was disabled. dl2 does not react. overvoltage protection can be disabled through the no- fault test mode (see the no-fault test mode section). output undervoltage protection if the MAX17030/max17036 output voltage is 400mv below the target voltage, the controller activates the shutdown sequence and sets the fault latch. once the output voltage ramps down to 12.5mv, it forces the dl1 and dl2 low and pulls dh1 and dh2 low, three-states pwm3, and sets drskp low 10 ? csni discharge fet is turned on. toggle shdn or cycle the v cc power supply below 0.5v to clear the fault latch and reactivate the controller. uvp can be disabled through the no-fault test mode (see the no-fault test mode section). thermal-fault protection the MAX17030/max17036 feature a thermal fault-pro- tection circuit. when the junction temperature rises above +160c, a thermal sensor sets the fault latch and forces the dl1 and dl2 low and pulls dh1 and dh2 low, three-states pwm3, sets drskp low, and enables 10 ? csni discharge fet on. toggle shdn or cycle the v cc power supply below 0.5v to clear the fault latch and reactivate the controller after the junction tempera- ture cools by 15c. thermal shutdown can be disabled through the no-fault test mode (see the no-fault test mode section). no-fault test mode the latched fault-protection features can complicate the process of debugging prototype breadboards since there are (at most) a few milliseconds in which to deter- mine what went wrong. therefore, a no-fault test mode is provided to disable the fault protectionover- voltage protection, undervoltage protection, and ther- mal shutdown. additionally, the test mode clears the fault latch if it has been set. the no-fault test mode is entered by forcing 11v to 13v on shdn . mosfet gate drivers the dh and dl drivers are optimized for driving moder- ate-sized high-side and larger low-side power mosfets. this is consistent with the low duty factor seen in notebook applications, where a large v in - v out differential exists. the high-side gate drivers (dh) source 2.7a and sink 2.2a, and the low-side gate dri- vers (dl) source 2.7a and sink 8a. this ensures robust gate drive for high-current applications. the dh_ float- ing high-side mosfet drivers are powered by internal boost switch charge pumps at bst_, while the dl_ syn- chronous-rectifier drivers are powered directly by the 5v bias supply (v dd ). adaptive dead-time circuits monitor the dl and dh dri- vers and prevent either fet from turning on until the other is fully off. the adaptive driver dead time allows operation without shoot-through with a wide range of mosfets, minimizing delays and maintaining efficiency. a low-resistance, low-inductance path from the dl and dh drivers to the mosfet gates is required for the adaptive dead-time circuits to work properly; otherwise, the sense circuitry in the MAX17030/max17036 inter- prets the mosfet gates as off while charge actually remains. use very short, wide traces (50 mils to 100 mils wide if the mosfet is 1in from the driver). the dl low on-resistance of 0.25 ? (typ) helps prevent dl from being pulled up due to capacitive coupling from the drain to the gate of the low-side mosfets when the inductor node (lx) quickly switches from ground to v in . the capacitive coupling between lx and dl created by the mosfets gate-to-drain capacitance (c rss ), gate- to-source capacitance (c iss - c rss ), and additional board parasitics should not exceed the following mini- mum threshold to prevent shoot-through currents: adding a 4700pf between dl and power ground (c nl in figure 10), close to the low-side mosfets, greatly reduces coupling. do not exceed 22nf of total gate capacitance to prevent excessive turn-off delays. vv c c gs th in max rss iss () ( ) > ? ? ? ? ? ?
MAX17030/max17036 1/2/3-phase quick-pwm imvp-6.5 vid controllers ______________________________________________________________________________________ 33 shoot-through currents can also be caused by a com- bination of fast high-side mosfets and slow low-side mosfets. if the turn-off delay time of the low-side mosfet is too long, the high-side mosfets can turn on before the low-side mosfets have actually turned off. adding a resistor less than 5 ? in series with bst slows down the high-side mosfet turn-on time, elimi- nating the shoot-through currents without degrading the turn-off time (r bst in figure 10). slowing down the high-side mosfet also reduces the lx node rise time, thereby reducing emi and high-frequency coupling responsible for switching noise. multiphase quick-pwm design procedure firmly establish the input voltage range and maximum load current before choosing a switching frequency and inductor operating point (ripple-current ratio). the pri- mary design trade-off lies in choosing a good switching frequency and inductor operating point, and the following four factors dictate the rest of the design: input voltage range: the maximum value (v in(max) ) must accommodate the worst-case high ac adapter voltage. the minimum value (v in(min) ) must account for the lowest input voltage after drops due to connectors, fuses, and battery selec- tor switches. if there is a choice at all, lower input voltages result in better efficiency. maximum load current: there are two values to consider. the peak load current (i load(max) ) deter- mines the instantaneous component stresses and filtering requirements, and thus drives output capacitor selection, inductor saturation rating, and the design of the current-limit circuit. the continu- ous load current (i load ) determines the thermal stresses and thus drives the selection of input capacitors, mosfets, and other critical heat-con- tributing components. modern notebook cpus gen- erally exhibit i load = i load(max) x 80%. for multiphase systems, each phase supports a fraction of the load, depending on the current bal- ancing. when properly balanced, the load current is evenly distributed among each phase: where total is the total number of active phases. switching frequency: this choice determines the basic trade-off between size and efficiency. the optimal frequency is largely a function of maximum input voltage, due to mosfet switching losses that are proportional to frequency and v in 2 . the opti- mum frequency is also a moving target, due to rapid improvements in mosfet technology that are making higher frequencies more practical. inductor operating point: this choice provides trade-offs between size vs. efficiency and transient response vs. output noise. low inductor values pro- vide better transient response and smaller physical size, but also result in lower efficiency and higher output noise due to increased ripple current. the minimum practical inductor value is one that causes the circuit to operate at the edge of critical conduc- tion (where the inductor current just touches zero with every cycle at maximum load). inductor values lower than this grant no further size-reduction bene- fit. the optimum operating point is usually found between 30% and 50% ripple current. for a multi- phase core regulator, select an lir value of ~0.4. inductor selection the switching frequency and operating point (% ripple current or lir) determine the inductor value as follows: where total is the total number of phases. l vv fi lir v v total in out sw load max out = ? ? ? ? ? ? ? () i in ? ? ? ? ? ? i i load phase load total () = bst_ dh_ lx_ (r bst )* input (v in ) c bst n h c byp l (r bst )* optional?the resistor lowers emi by decreasing the switching node rise time. (c nl )* optional?the capacitor reduces lx to dl capacitive coupling that can cause shoot-through current. dl_ pgnd n l (c nl )* v dd MAX17030/max17036 figure 10. gate drive circuit
MAX17030/max17036 1/2/3-phase quick-pwm imvp-6.5 vid controllers 34 ______________________________________________________________________________________ find a low-loss inductor having the lowest possible dc resistance that fits in the allotted dimensions. the core must not to saturate at the peak inductor current (i peak ): output capacitor selection output capacitor selection is determined by the con- troller stability requirements, and the transient soar and sag requirements of the application. output capacitor esr the output filter capacitor must have low enough effec- tive series resistance (esr) to meet output ripple and load-transient requirements, yet have high enough esr to satisfy stability requirements. in cpu v core converters and other applications where the output is subject to large load transients, the output capacitors size typically depends on how much esr is needed to prevent the output from dipping too low under a load transient. ignoring the sag due to finite capacitance: the output ripple voltage of a step-down controller equals the total inductor ripple current multiplied by the output capacitors esr. when operating multiphase systems out-of-phase, the peak inductor currents of each phase are staggered, resulting in lower output rip- ple voltage by reducing the total inductor ripple current. for multiphase operation, the maximum esr to meet ripple requirements is: where total is the total number of active phases and f sw is the switching frequency per phase. the actual capacitance value required relates to the physical size needed to achieve low esr, as well as to the chemistry of the capacitor technology. thus, the capacitor is usu- ally selected by esr and voltage rating rather than by capacitance value (this is true of polymer types). when using low-capacity ceramic filter capacitors, capacitor size is usually determined by the capacity needed to prevent v sag and v soar from causing prob- lems during load transients. generally, once enough capacitance is added to meet the overshoot require- ment, undershoot at the rising load edge is no longer a problem (see the v sag and v soar equations in the transient response section). output capacitor stability considerations for quick-pwm controllers, stability is determined by the value of the esr zero relative to the switching fre- quency. the boundary of instability is given by the fol- lowing equation: where: and: where c out is the total output capacitance, r esr is the total equivalent series resistance, r droop is the volt- age-positioning gain, and r pcb is the parasitic board resistance between the output capacitors and sense resistors. for a standard 300khz application, the esr zero fre- quency must be well below 95khz, preferably below 50khz. tantalum, sanyo poscap, and panasonic sp capacitors in widespread use at the time of publication have typical esr zero frequencies below 50khz. in the standard application circuit, the esr needed to support a 30mv p-p ripple is 30mv/(40a x 0.3) = 2.5m ? . four 330f/2.5v panasonic sp (type sx) capacitors in paral- lel provide 1.5m ? (max) esr. with a 2m ? droop and 0.5m ? pcb resistance, the typical combined esr results in a zero at 30khz. ceramic capacitors have a high esr zero frequency, but applications with significant voltage positioning can take advantage of their size and low esr. when using only ceramic output capacitors, output overshoot (v soar ) typically determines the minimum output capacitance requirement. their relatively low capacitance value favors high switching-frequency operation with small inductor values to minimize the energy transferred from inductor to capacitor during load-step recovery. unstable operation manifests itself in two related but distinctly different ways: double-pulsing and feedback loop instability. double pulsing occurs due to noise on the output or because the esr is so low that there is not enough voltage ramp in the output-voltage signal. this fools the error comparator into triggering a new cycle immediately after the minimum off-time period has expired. double pulsing is more annoying than harmful, resulting in nothing worse than increased output ripple. rrr r eff esr droop pcb =+ + f rc esr eff out = 1 2 f f esr sw r vf l vvv v esr in sw in total out out ri ? () ? ? ? ? ? ? ? ? p pple rr v i esr pcb step load max + () ? () i i lir peak load max total = ? ? ? ? ? ? + ? ? ? ? ? ? () 1 2
MAX17030/max17036 1/2/3-phase quick-pwm imvp-6.5 vid controllers ______________________________________________________________________________________ 35 however, it can indicate the possible presence of loop instability due to insufficient esr. loop instability can result in oscillations at the output after line or load steps. such perturbations are usually damped, but can cause the output voltage to rise above or fall below the tolerance limits. the easiest method for checking stability is to apply a very fast 10% to 90% max load transient and carefully observe the output voltage ripple envelope for over- shoot and ringing. it can help to simultaneously monitor the inductor current with an ac current probe. do not allow more than one cycle of ringing after the initial step-response under/overshoot. transient response the inductor ripple current impacts transient-response performance, especially at low v in - v out differentials. low inductor values allow the inductor current to slew faster, replenishing charge removed from the output fil- ter capacitors by a sudden load step. the amount of output sag is also a function of the maximum duty fac- tor, which can be calculated from the on-time and mini- mum off-time. for a dual-phase controller, the worst-case output sag voltage can be determined by: and: where t off(min) is the minimum off-time (see the electrical characteristics ), t sw is the programmed switching period, and total is the total number of active phases. k = 66% when n ph = 3, and k = 100% when n ph = 2. v sag must be less than the transient droop ? i load(max) x r droop . the capacitive soar voltage due to stored inductor energy can be calculated as: where total is the total number of active phases. the actual peak of the soar voltage is dependent on the time where the decaying esr step and rising capaci- tive soar is at its maximum. this is best simulated or measured. for the max17036 with transient suppres- sion, contact maxim directly for application support to determine the output capacitance requirement. input capacitor selection the input capacitor must meet the ripple current requirement (i rms ) imposed by the switching currents. the multiphase quick-pwm controllers operate out-of- phase, reducing the rms input. for duty cycles less than 100%/ outph per phase, the i rms requirements can be determined by the following equation: where total is the total number of out-of-phase switching regulators. the worst-case rms current requirement occurs when operating with v in = 2 total v out . at this point, the above equation simpli- fies to i rms = 0.5 x i load / total . choose an input capacitor that exhibits less than +10 c temperature rise at the rms input current for optimal circuit longevity. power-mosfet selection most of the following mosfet guidelines focus on the challenge of obtaining high load-current capability when using high-voltage (> 20v) ac adapters. high-side mosfet power dissipation the conduction loss in the high-side mosfet (n h ) is a function of the duty factor, with the worst-case power dissipation occurring at the minimum input voltage: where total is the total number of phases. calculating the switching losses in the high-side mosfet (n h ) is difficult since it must allow for difficult quantifying factors that influence the turn-on and turn- off times. these factors include the internal gate resis- tance, gate charge, threshold voltage, source inductance, and pcb layout characteristics. the follow- ing switching-loss calculation provides only a very rough estimate and is no substitute for breadboard evaluation, preferably including verification using a thermocouple mounted on n h : where c oss is the n h mosfets output capacitance, q g(sw) is the charge needed to turn on the n h mosfet, and i gate is the peak gate-drive source/sink current (2.2a typ). pd (nh switching) = vi f in load sw total ? ? ? ? ? ? q q i gsw gate () ? ? ? ? ? ? + cvf oss in sw 2 2 pd (nh resistive) = v v i out in load tota ? ? ? ? ? ? l l ds on r ? ? ? ? ? ? 2 () i i v vv rms load total in total out in tot = ? ? ? ? ? ? ? ? a al out v () v il cv soar load max total out out () ? () 2 2 ttt min on off min =+ () v cv t kt sag total out out min () li load(max) 2 ? 2 s sw min t ? ? ? ? ?
MAX17030/max17036 1/2/3-phase quick-pwm imvp-6.5 vid controllers 36 ______________________________________________________________________________________ the optimum high-side mosfet trades the switching losses with the conduction (r ds(on) ) losses over the input voltage range. ideally, the losses at v in(min) should be roughly equal to losses at v in(max) , with lower losses in between. if v in does not vary over a wide range, the minimum power dissipation occurs where the resistive losses equal the switching losses. low-side mosfet power dissipation for the low-side mosfet (n l ), the worst-case power dissipation always occurs at maximum input voltage: the worst case for mosfet power dissipation occurs under heavy overloads that are greater than i load(max) but are not quite high enough to exceed the current limit and cause the fault latch to trip. to protect against this possibility, the circuit can be overdesigned to tolerate: where i valley(max) is the maximum valley current allowed by the current-limit circuit, including threshold tolerance and on-resistance variation. the mosfets must have a good-size heatsink to handle the overload power dissipation. choose a low-side mosfet that has the lowest possible on-resistance (r ds(on) ), comes in a moderate-sized package (i.e., one or two thermally enhanced 8-pin sos), and is reasonably priced. make sure that the dl gate dri- ver can supply sufficient current to support the gate charge and the current injected into the parasitic gate-to- drain capacitor caused by the high-side mosfet turning on; otherwise, cross-conduction problems might occur (see the mosfet gate drivers section). the optional schottky diode (d l ) should have a low for- ward voltage and be able to handle the load current per phase during the dead times. boost capacitors the boost capacitors (c bst ) must be selected large enough to handle the gate-charging requirements of the high-side mosfets. select the boost capacitors to avoid discharging the capacitor more than 200mv while charging the high-side mosfets gates: where n is the number of high-side mosfets used for one regulator, and q gate is the gate charge specified in the mosfets data sheet. for example, assume (1) fds6298 n-channel mosfets are used on the high side. according to the manufacturers data sheet, a sin- gle fds6298 has a maximum gate charge of 19nc (v gs = 5v). using the above equation, the required boost capacitance would be: selecting the closest standard value; this example requires a 0.1f ceramic capacitor. current limit and slew-rate control (time and ilim) time and ilim are used to control the slew rate and current limit. time regulates to a fixed 2.0v. the MAX17030/max17036 use the time source current to set the slew rate (dv target /dt). the higher the source current, the faster the output-voltage slew rate: where r time is the sum of resistance values between time and ground. the ilim voltage determines the valley current-sense threshold. when ilim = v cc , the controller uses the 22.5mv preset current-limit threshold. in an adjustable design, ilim is connected to a resistive voltage- divider connected between time and ground. the dif- ferential voltage between time and ilim sets the cur- rent-limit threshold (v limit ), so the valley current-sense threshold: this allows design flexibility since the dcr sense circuit or sense resistor does not have to be adjusted to meet the current limit as long as the current-sense voltage never exceeds 50mv. keeping v limit between 20mv to 40mv leaves room for future current-limit adjustment. the minimum current-limit threshold must be high enough to support the maximum load current when the current limit is at the minimum tolerance value. the val- ley of the inductor current occurs at i load(max) minus half the ripple current; therefore: ii lir valley load max >? ? ? ? ? ? ? () 1 2 v vv limit time ilim = ? 10 dv dt mv s k r target time = ? ? ? ? ? ? 12 5 71 5 . . ? c nc mv f bst = = 110 200 005 . c nq mv bst gate = 200 ii i load total valley max inductor =+ ? ? ? ? ? ? () ? 2 () () =+ total valley max load max i ilir 2 2 ? ? ? ? ? ? pd (nl resistive) = 1 ? ? ? ? ? ? ? ? ? ? ? v v out in max () ? ? ? ? ? ? ? ? ? ? ? i r load total ds on 2 ()
MAX17030/max17036 1/2/3-phase quick-pwm imvp-6.5 vid controllers ______________________________________________________________________________________ 37 where: where r sense is the sensing resistor or effective induc- tor dcr. voltage positioning and loop compensation voltage positioning dynamically lowers the output volt- age in response to the load current, reducing the out- put capacitance and processors power-dissipation requirements. the MAX17030/max17036 use a transconductance amplifier to set the transient and dc output voltage droop (figure 3) as a function of the load. this adjustability allows flexibility in the selected current-sense resistor value or inductor dcr, and allows smaller current-sense resistance to be used, reducing the overall power dissipated. steady-state voltage positioning connect a resistor (r fb ) between fb and v out to set the dc steady-state droop (load line) based on the required voltage-positioning slope (r droop ): where the effective current-sense resistance (r sense ) depends on the current-sense method (see the current sense section), and the voltage positioning amplifiers transconductance (g m(fb) ) is typically 400s as defined in the electrical characteristics table. the con- troller sums together the input signals of the current- sense inputs (csp_, csn_). when the inductors dcr is used as the current-sense element (r sense = r dcr ), each current-sense input should include an ntc thermistor to minimize the tem- perature dependence of the voltage-positioning slope. applications information pcb layout guidelines careful pcb layout is critical to achieve low switching losses and clean, stable operation. the switching power stage requires particular attention. if possible, mount all the power components on the top side of the board with their ground terminals flush against one another. refer to the MAX17030 evaluation kit specifi- cation for a layout example and follow these guidelines for good pcb layout: 1) keep the high-current paths short, especially at the ground terminals. this is essential for stable, jitter- free operation. 2) connect all analog grounds to a separate solid cop- per plane, which connects to the ground pin of the quick-pwm controller. this includes the v cc bypass capacitor, fb, and gnds bypass capacitors. 3) keep the power traces and load connections short. this is essential for high efficiency. the use of thick copper pcb (2oz vs. 1oz) can enhance full-load efficiency by 1% or more. correctly routing pcb traces is a difficult task that must be approached in terms of fractions of centimeters, where a single m ? of excess trace resistance causes a measurable efficiency penalty. 4) keep the high current, gate-driver traces (dl, dh, lx, and bst) short and wide to minimize trace resistance and inductance. this is essential for high-power mosfets that require low-impedance gate drivers to avoid shoot-through currents. 5) csp_ and csn_ connections for current limiting and voltage positioning must be made using kelvin sense connections to guarantee the current-sense accuracy. 6) when trade-offs in trace lengths must be made, it is preferable to allow the inductor charging path to be made longer than the discharge path. for example, it is better to allow some extra distance between the input capacitors and the high-side mosfet than to allow distance between the inductor and the low- side mosfet or between the inductor and the out- put filter capacitor. 7) route high-speed switching nodes away from sen- sitive analog areas (fb, csp_, csn_, etc.). layout procedure 1) place the power components first, with ground ter- minals adjacent (low-side mosfet source, c in , c out , and d1 anode). if possible, make all these connections on the top layer with wide, copper- filled areas. 2) mount the controller ic adjacent to the low-side mosfet. the dl gate traces must be short and wide (50mils to 100mils wide if the mosfet is 1in from the controller ic). 3) group the gate-drive components (bst diodes and capacitors, v dd bypass capacitor) together near the controller ic. r r rg fb droop sense m fb = () i v r valley limit sense =
MAX17030/max17036 1/2/3 phase-quick-pwm imvp-6.5 vid controllers maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 38 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ? 2008 maxim integrated products is a registered trademark of maxim integrated products, inc. package information for the latest package outline information and land patterns, go to www.maxim-ic.com/packages . package type package code document no. 40 tqfn-ep t4055-2 21-0140 chip information process: bicmos 4) make the dc-dc controller ground connections as shown in the standard application circuits. this dia- gram can be viewed as having four separate ground planes: input/output ground, where all the high- power components go; the power ground plane, where the gnd pin and v dd bypass capacitor go; the masters analog ground plane, where sensitive analog components, the masters gnd pin and v cc bypass capacitor go; and the slaves analog ground plane, where the slaves gnd pin and v cc bypass capacitor go. the masters gnd plane must meet the gnd plane only at a single point directly beneath the ic. similarly, the slaves gnd plane must meet the gnd plane only at a single point directly beneath the ic. the respective master and slave ground planes should connect to the high- power output ground with a short metal trace from gnd to the source of the low-side mosfet (the middle of the star ground). this point must also be very close to the output capacitor ground terminal. 5) connect the output power planes (v core and sys- tem ground planes) directly to the output filter capacitor positive and negative terminals with multi- ple vias. place the entire dc-dc converter circuit as close to the cpu as is practical.

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